Inventor · disambiguated record
Niket K. Choudhary
Also filed as: CHOUDHARY NIKET · CHOUDHARY NIKET K · CHOUDHARY NIKET KUMAR
16 granted patents·13 pending applications·8 citations·filing 2013–2025
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
29 records- 0189US12067399B2Conditional instructions predictionAPPLE INC·Filed 2022·Granted Aug 20, 2024·2 cites·20 claims
- 0289US11809874B2Conditional instructions distribution and execution on pipelines having different latencies for mispredictionsAPPLE INC·Filed 2022·Granted Nov 7, 2023·2 cites·20 claims
- 0388US12229561B1Processing of data synchronization barrier instructionsAPPLE INC·Filed 2022·Granted Feb 18, 2025·2 cites·20 claims
- 0478US11550723B2Method, apparatus, and system for memory bandwidth aware data prefetchingQUALCOMM INC·Filed 2018·Granted Jan 10, 2023·2 cites·26 claims
- 0578US2025362918A1Sharing Branch Predictor Resource for Instruction Cache and Trace Cache PredictionsAPPLE INC·Filed 2025·Application pending·0 cites
- 0675US2025321744A1Using a Next Fetch Predictor Circuit with Short Branches and Return Fetch GroupsAPPLE INC·Filed 2025·Application pending·0 cites
- 0773US2025278277A1Re-use of Speculative Control Transfer Instruction Results from Wrong PathAPPLE INC·Filed 2025·Application pending·0 cites
- 0871US2024385842A1Conditional Instructions PredictionAPPLE INC·Filed 2024·Application pending·0 cites
- 0969US12436766B2Sharing branch predictor resource for instruction cache and trace cache predictionsAPPLE INC·Filed 2023·Granted Oct 7, 2025·0 cites·20 claims
- 1068US12321751B2Re-use of speculative control transfer instruction results from wrong pathAPPLE INC·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 1165US12373215B2Using a next fetch predictor circuit with short branches and return fetch groupsAPPLE INC·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 1263US2025147767A1Processing of Data Synchronization Barrier InstructionsAPPLE INC·Filed 2025·Application pending·0 cites
- 1361US12265823B2Trace cache with filter for internal control transfer inclusionAPPLE INC·Filed 2023·Granted Apr 1, 2025·0 cites·20 claims
- 1457US12175248B2Re-use of speculative load instruction results from wrong pathAPPLE INC·Filed 2023·Granted Dec 24, 2024·0 cites·20 claims
- 1556US12353882B1Next fetch prediction using historyAPPLE INC·Filed 2023·Granted Jul 8, 2025·0 cites·17 claims
- 1655US12423106B2Next fetch predictor for trace cacheAPPLE INC·Filed 2023·Granted Sep 23, 2025·0 cites·20 claims
- 1754US12236244B1Multi-degree branch predictorAPPLE INC·Filed 2022·Granted Feb 25, 2025·0 cites·20 claims
- 1851US12326819B1Renaming context identifiers in a processorAPPLE INC·Filed 2023·Granted Jun 10, 2025·0 cites·20 claims
- 1951US11061822B2Method, apparatus, and system for reducing pipeline stalls due to address translation missesQUALCOMM INC·Filed 2018·Granted Jul 13, 2021·0 cites·24 claims
- 2051US2025315262A1Hierarchical Trace CacheAPPLE INC·Filed 2024·Application pending·0 cites
- 2149US10877895B2Method, apparatus, and system for prefetching exclusive cache coherence state for store instructionsQUALCOMM INC·Filed 2018·Granted Dec 29, 2020·0 cites·23 claims
- 2247US9471325B2Method and apparatus for selective renaming in a microprocessorQUALCOMM INC·Filed 2013·Granted Oct 18, 2016·0 cites·30 claims
- 2344US2015268959A1Physical register scrubbing in a computer microprocessorQUALCOMM INC·Filed 2014·Application pending·0 cites
- 2443US2019370176A1Adaptively predicting usefulness of prefetches generated by hardware prefetch engines in processor-based devicesQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2543US2014281439A1Hardware optimization of hard-to-predict short forward branchesQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2639US2019294443A1Providing early pipeline optimization of conditional instructions in processor-based systemsQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2735US2017083333A1Branch target instruction cache (btic) to store a conditional branch instructionQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2835US2017060593A1Hierarchical register file systemQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2931US2016335089A1Eliminating redundancy in a branch target instruction cache by establishing entries using the target address of a subroutineQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →