Inventor · disambiguated record
Nicolas Daval
Also filed as: DAVAL NICOLAS
25 granted patents·8 pending applications·154 citations·filing 2003–2025
95Inventor score
Files withSOITEC SILICON ON INSULATOR24DAVAL NICOLAS5BEDELL STEPHEN W1COMMISSARIAT ENERGIE ATOMIQUE1DELATTRE CECILE1
Top patents by PatentIndex Score
33 records- 0192US10957577B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2017·Granted Mar 23, 2021·7 cites·18 claims
- 0292US6991956B2Methods for transferring a thin layer from a wafer having a buffer layerSOITEC SILICON ON INSULATOR·Filed 2005·Granted Jan 31, 2006·23 cites·23 claims
- 0391US7459374B2Method of manufacturing a semiconductor heterostructureSOITEC SILICON ON INSULATOR·Filed 2007·Granted Dec 2, 2008·19 cites·17 claims
- 0490US7449394B2Atomic implantation and thermal treatment of a semiconductor layerSOITEC SILICON ON INSULATOR·Filed 2005·Granted Nov 11, 2008·20 cites·19 claims
- 0589US7232737B2Treatment of a removed layer of silicon-germaniumSOITEC SILICON ON INSULATOR·Filed 2005·Granted Jun 19, 2007·15 cites·20 claims
- 0687US8367521B2Manufacture of thin silicon-on-insulator (SOI) structuresSOITEC SILICON ON INSULATOR·Filed 2010·Granted Feb 5, 2013·8 cites·18 claims
- 0787US7446019B2Method of reducing roughness of a thick insulating layerSOITEC SILICON ON INSULATOR·Filed 2006·Granted Nov 4, 2008·10 cites·17 claims
- 0883US12261079B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2023·Granted Mar 25, 2025·0 cites·19 claims
- 0982US7282449B2Thermal treatment of a semiconductor layerSOITEC SILICON ON INSULATOR·Filed 2006·Granted Oct 16, 2007·8 cites·21 claims
- 1078US2025239483A1Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2025·Application pending·0 cites
- 1177US7276428B2Methods for forming a semiconductor structureSOITEC SILICON ON INSULATOR·Filed 2005·Granted Oct 2, 2007·7 cites·22 claims
- 1276US7531427B2Thermal oxidation of a SiGe layer and applications thereofSOITEC SILICON ON INSULATOR·Filed 2007·Granted May 12, 2009·5 cites·24 claims
- 1372US11728207B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2021·Granted Aug 15, 2023·0 cites·20 claims
- 1472US7166894B2Schottky power diode with SiCOI substrate and process for making such diodeCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2003·Granted Jan 23, 2007·15 cites·14 claims
- 1572US2025015122A1Structure for a front-facing image sensorSOITEC SILICON ON INSULATOR·Filed 2024·Application pending·0 cites
- 1669US11876020B2Method for manufacturing a CFET deviceSOITEC SILICON ON INSULATOR·Filed 2019·Granted Jan 16, 2024·1 cites·20 claims
- 1769US7645486B2Method of manufacturing a silicon dioxide layerSOITEC SILICON ON INSULATOR·Filed 2007·Granted Jan 12, 2010·3 cites·20 claims
- 1869US2024145314A1Complementary field-effect transistor device including at least one finSOITEC SILICON ON INSULATOR·Filed 2024·Application pending·0 cites
- 1968US7285495B2Methods for thermally treating a semiconductor layerSOITEC SILICON ON INSULATOR·Filed 2005·Granted Oct 23, 2007·4 cites·19 claims
- 2065US10672646B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2017·Granted Jun 2, 2020·1 cites·19 claims
- 2163US7078353B2Indirect bonding with disappearance of bonding layerSOITEC SILICON ON INSULATOR·Filed 2004·Granted Jul 18, 2006·8 cites·21 claims
- 2259US8753528B2Etchant for controlled etching of Ge and Ge-rich silicon germanium alloysIBM·Filed 2013·Granted Jun 17, 2014·0 cites·13 claims
- 2356US12100727B2Method for manufacturing a substrate for a front-facing image sensorSOITEC SILICON ON INSULATOR·Filed 2019·Granted Sep 24, 2024·0 cites·18 claims
- 2453US8183128B2Method of reducing roughness of a thick insulating layerDAVAL NICOLAS·Filed 2008·Granted May 22, 2012·0 cites·21 claims
- 2551US2012091100A1Etchant for controlled etching of ge and ge-rich silicon germanium alloysBEDELL STEPHEN W·Filed 2010·Application pending·0 cites
- 2648US2011183493A1Process for manufacturing a structure comprising a germanium layer on a substrateSOITEC SILICON ON INSULATOR·Filed 2009·Application pending·0 cites
- 2741US9177961B2Wafer with intrinsic semiconductor layerDAVAL NICOLAS·Filed 2012·Granted Nov 3, 2015·0 cites·17 claims
- 2841US9018678B2Method for forming a Ge on III/V-on-insulator structureDAVAL NICOLAS·Filed 2012·Granted Apr 28, 2015·0 cites·13 claims
- 2937US2006014363A1Thermal treatment of a semiconductor layerDAVAL NICOLAS·Filed 2005·Application pending·0 cites
- 3036US2006270244A1Method of fabricating a structure with an oxide layer of a desired thickness on a Ge or SiGe substrateDAVAL NICOLAS·Filed 2005·Application pending·0 cites
- 3135US2007111474A1Treating a SiGe layer for selective etchingDELATTRE CECILE·Filed 2006·Application pending·0 cites
- 3233US9768057B2Method for transferring a layer from a single-crystal substrateSOITEC SILICON ON INSULATOR·Filed 2016·Granted Sep 19, 2017·0 cites·7 claims
- 3331US7452792B2Relaxation of layersSOITEC SILICON ON INSULATOR·Filed 2006·Granted Nov 18, 2008·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →