Inventor · disambiguated record
Niels Fricke
Also filed as: FRICKE NIELS
20 granted patents·1 pending application·27 citations·filing 2008–2022
90Inventor score
Top patents by PatentIndex Score
21 records- 0195US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0287US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 0387US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 0483US9418198B1Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)IBM·Filed 2015·Granted Aug 16, 2016·4 cites·12 claims
- 0581US9536030B2Optimization of integrated circuit physical designIBM·Filed 2014·Granted Jan 3, 2017·8 cites·20 claims
- 0664US8522187B2Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program productFRICKE NIELS·Filed 2011·Granted Aug 27, 2013·3 cites·14 claims
- 0763US10996953B2Low latency execution of floating-point record form instructionsIBM·Filed 2019·Granted May 4, 2021·0 cites·7 claims
- 0860US10768897B2Arithmetic logic unit for single-cycle fusion operationsIBM·Filed 2019·Granted Sep 8, 2020·0 cites·20 claims
- 0958US10678547B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Jun 9, 2020·0 cites·7 claims
- 1058US10592246B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Mar 17, 2020·0 cites·10 claims
- 1156US11157276B2Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entryIBM·Filed 2019·Granted Oct 26, 2021·0 cites·19 claims
- 1254US10545727B2Arithmetic logic unit for single-cycle fusion operationsIBM·Filed 2018·Granted Jan 28, 2020·0 cites·14 claims
- 1351US11093246B2Banked slice-target register file for wide dataflow execution in a microprocessorIBM·Filed 2019·Granted Aug 17, 2021·0 cites·18 claims
- 1451US10360036B2Cracked execution of move-to-FPSCR instructionsIBM·Filed 2017·Granted Jul 23, 2019·0 cites·20 claims
- 1551US9727687B2Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)IBM·Filed 2015·Granted Aug 8, 2017·0 cites·6 claims
- 1650US12411996B2Hardware-based implementation of secure hash algorithmsIBM·Filed 2022·Granted Sep 9, 2025·0 cites·16 claims
- 1749US10831496B2Method to execute successive dependent instructions from an instruction stream in a processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 1848US11561798B2On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result bufferIBM·Filed 2020·Granted Jan 24, 2023·0 cites·20 claims
- 1946US12288064B2Hardware-based message block padding for hash algorithmsIBM·Filed 2022·Granted Apr 29, 2025·0 cites·20 claims
- 2046US11182167B2Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threadsIBM·Filed 2019·Granted Nov 23, 2021·0 cites·14 claims
- 2131US2008272817A1Integrated Circuit on a Semiconductor Chip with a Phase Shift Circuit and a Method for Digital Phase ShiftingFRICKE NIELS·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →