Inventor · disambiguated record
Nikhil Jayakumar
Also filed as: JAYAKUMAR NIKHIL
13 granted patents·1 pending application·15 citations·filing 2010–2022
84Inventor score
Top patents by PatentIndex Score
14 records- 0194US11340673B1System and method to manage power throttlingMARVELL ASIA PTE LTD·Filed 2020·Granted May 24, 2022·5 cites·25 claims
- 0278US9443053B2System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networksXPLIANT INC·Filed 2013·Granted Sep 13, 2016·7 cites·23 claims
- 0369US11687136B2System and method to manage power throttlingMARVELL ASIA PTE LTD·Filed 2022·Granted Jun 27, 2023·0 cites·27 claims
- 0460US9600620B2Repeater insertions providing reduced routing perturbation caused by flip-flop insertionsXpliant·Filed 2015·Granted Mar 21, 2017·1 cites·17 claims
- 0553US7880505B2Low power reconfigurable circuits with delay compensationKHATRI SUNIL PAPANCHAND·Filed 2010·Granted Feb 1, 2011·2 cites·27 claims
- 0650US12033903B1High-density microbump and probe pad arrangement for semiconductor componentsAMAZON TECH INC·Filed 2021·Granted Jul 9, 2024·0 cites·16 claims
- 0745US10198389B2Baseboard interconnection device, system and methodCAVIUM INC·Filed 2014·Granted Feb 5, 2019·0 cites·25 claims
- 0844US11994925B2Power management and staggering transitioning from idle mode to operational modeMARVELL ASIA PTE LTD·Filed 2020·Granted May 28, 2024·0 cites·33 claims
- 0944US9390209B2System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networksXPLIANT INC·Filed 2013·Granted Jul 12, 2016·0 cites·22 claims
- 1044US2016014885A1Network device, system and method having a rotated chip floorplanXPLIANT INC·Filed 2014·Application pending·0 cites
- 1142US9305129B2System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cellsXPLIANT INC·Filed 2013·Granted Apr 5, 2016·0 cites·30 claims
- 1241US10303626B2Approach for chip-level flop insertion and verification based on logic interface definitionCAVIUM LLC·Filed 2015·Granted May 28, 2019·0 cites·36 claims
- 1337US9600614B2Automated flip-flop insertions in physical design without perturbation of routingXpliant·Filed 2015·Granted Mar 21, 2017·0 cites·20 claims
- 1436US9792400B2Determination of flip-flop count in physical designXpliant·Filed 2015·Granted Oct 17, 2017·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →