Inventor · disambiguated record
Norman J. Rasmussen
Also filed as: RASMUSSEN NORMAN · RASMUSSEN NORMAN J
19 granted patents·751 citations·filing 1992–2002
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
19 records- 0188US5822767AMethod and apparartus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Oct 13, 1998·109 cites·11 claims
- 0283US6112016AMethod and apparatus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Aug 29, 2000·83 cites·16 claims
- 0381US5809340AAdaptively generating timing signals for access to various memory devices based on stored profilesPACKARD BELL NEC·Filed 1997·Granted Sep 15, 1998·99 cites·5 claims
- 0480US5467295ABus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unitINTEL CORP·Filed 1992·Granted Nov 14, 1995·73 cites·23 claims
- 0579US6502146B1Apparatus and method for dedicated interconnection over a shared external busINTEL CORP·Filed 2000·Granted Dec 31, 2002·24 cites·25 claims
- 0677US5768548ABus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored dataINTEL CORP·Filed 1997·Granted Jun 16, 1998·82 cites·17 claims
- 0770US6317803B1High-throughput interconnect having pipelined and non-pipelined bus transaction modesINTEL CORP·Filed 1996·Granted Nov 13, 2001·57 cites·35 claims
- 0868US5887194ALocking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains lockedINTEL CORP·Filed 1995·Granted Mar 23, 1999·44 cites·9 claims
- 0968US5651137AScalable cache attributes for an input/output busINTEL CORP·Filed 1995·Granted Jul 22, 1997·42 cites·24 claims
- 1065US6594717B2Apparatus and method for dedicated interconnection over a shared external busINTEL CORP·Filed 2002·Granted Jul 15, 2003·9 cites·7 claims
- 1163US6266719B1High-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 2000·Granted Jul 24, 2001·6 cites·5 claims
- 1259US6434692B2High-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 2001·Granted Aug 13, 2002·4 cites·33 claims
- 1357US5948094AMethod and apparatus for executing multiple transactions within a single arbitration cycleINTEL CORP·Filed 1997·Granted Sep 7, 1999·32 cites·25 claims
- 1454US5740376ASignaling protocol for a peripheral component interconnectINTEL CORP·Filed 1997·Granted Apr 14, 1998·24 cites·8 claims
- 1553US6006291AHigh-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 1997·Granted Dec 21, 1999·18 cites·9 claims
- 1651US5832241AData consistency across a bus transactions that impose ordering constraintsINTEL CORP·Filed 1997·Granted Nov 3, 1998·27 cites·15 claims
- 1742US6047355ASymmetric multiprocessing system with unified environment and distributed system functionsINTEL CORP·Filed 1997·Granted Apr 4, 2000·8 cites·13 claims
- 1839US5522069ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1994·Granted May 28, 1996·7 cites·1 claims
- 1933US6167468AHigh-throughput interface between a system memory controller and a peripheral deviceINTEL CORP·Filed 1999·Granted Dec 26, 2000·3 cites·7 claims
Join the waitlist — get patent alerts
Get an alert when Norman J. Rasmussen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →