Inventor · disambiguated record
Oleg Margulis
Also filed as: MARGULIS OLEG
17 granted patents·4 pending applications·56 citations·filing 2008–2021
91Inventor score
Top patents by PatentIndex Score
21 records- 0188US8352683B2Method and system to reduce the power consumption of a memory deviceINTEL CORP·Filed 2010·Granted Jan 8, 2013·12 cites·16 claims
- 0282US8688917B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2012·Granted Apr 1, 2014·6 cites·18 claims
- 0381US8806101B2Metaphysical address space for holding lossy metadata in hardwareSHEAFFER GAD·Filed 2008·Granted Aug 12, 2014·10 cites·12 claims
- 0480US8627017B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·8 cites·25 claims
- 0577US8799582B2Extending cache coherency protocols to support locally buffered dataSHEAFFER GAD·Filed 2008·Granted Aug 5, 2014·8 cites·27 claims
- 0675US8769212B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2012·Granted Jul 1, 2014·3 cites·13 claims
- 0769US8271732B2System and method to reduce power consumption by partially disabling cache memoryCOHEN EHUD·Filed 2008·Granted Sep 18, 2012·5 cites·20 claims
- 0868US8627014B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·3 cites·29 claims
- 0966US10761849B2Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instructionINTEL CORP·Filed 2016·Granted Sep 1, 2020·1 cites·25 claims
- 1053US2022058294A1Integrated circuit to secure devices in the internet of thingsIUZIFOVICH IURII V·Filed 2021·Application pending·0 cites
- 1153US2022100909A1Method of securing devices used in the internet of thingsIUZIFOVICH IURII V·Filed 2021·Application pending·0 cites
- 1250US9727476B22-D gather instruction and a 2-D cacheINTEL CORP·Filed 2015·Granted Aug 8, 2017·0 cites·17 claims
- 1349US9001138B22-D gather instruction and a 2-D cacheGINZBURG BORIS·Filed 2011·Granted Apr 7, 2015·0 cites·23 claims
- 1448US10120686B2Eliminating redundant store instructions from execution while maintaining total store orderINTEL CORP·Filed 2016·Granted Nov 6, 2018·0 cites·20 claims
- 1547US10540178B2Eliminating redundant stores using a protection designator and a clear designatorINTEL CORP·Filed 2016·Granted Jan 21, 2020·0 cites·13 claims
- 1646US11194935B2Method of securing devices used in the internet of thingsIUZIFOVICH IURII V·Filed 2018·Granted Dec 7, 2021·0 cites·5 claims
- 1745US9996356B2Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processorINTEL CORP·Filed 2015·Granted Jun 12, 2018·0 cites·14 claims
- 1843US9710389B2Method and apparatus for memory aliasing detection in an out-of-order instruction execution platformINTEL CORP·Filed 2015·Granted Jul 18, 2017·0 cites·24 claims
- 1942US10853078B2Method and apparatus for supporting speculative memory optimizationsINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·20 claims
- 2040US2009300319A1Apparatus and method for memory structure to handle two load operationsCOHEN EHUD·Filed 2008·Application pending·0 cites
- 2136US2017192788A1Binary translation support using processor instruction prefixesINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →