Inventor · disambiguated record
Paul A. Bunce
Also filed as: BUNCE PAUL A · BUNCE PAUL ALAN
45 granted patents·4 pending applications·141 citations·filing 2001–2019
97Inventor score
Top patents by PatentIndex Score
49 records- 0193US9742408B1Dynamic decode circuit with active glitch controlIBM·Filed 2016·Granted Aug 22, 2017·8 cites·15 claims
- 0291US9966958B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted May 8, 2018·8 cites·12 claims
- 0385US7088638B1Global and local read control synchronization method and system for a memory array configured with multiple memory subarraysIBM·Filed 2005·Granted Aug 8, 2006·17 cites·26 claims
- 0485US7075855B1Memory output timing control circuit with merged functionsIBM·Filed 2005·Granted Jul 11, 2006·16 cites·18 claims
- 0583US7471590B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2007·Granted Dec 30, 2008·11 cites·5 claims
- 0681US10367507B2Dynamic decode circuit with active glitch controlIBM·Filed 2018·Granted Jul 30, 2019·3 cites·19 claims
- 0776US8345490B2Split voltage level restore and evaluate clock signals for memory address decodingIBM·Filed 2010·Granted Jan 1, 2013·6 cites·12 claims
- 0876US7283417B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2005·Granted Oct 16, 2007·8 cites·14 claims
- 0973US7085173B1Write driver circuit for memory arrayIBM·Filed 2005·Granted Aug 1, 2006·8 cites·12 claims
- 1068US8599642B2Port enable signal generation for gating a memory array device outputBUNCE PAUL A·Filed 2010·Granted Dec 3, 2013·3 cites·19 claims
- 1167US9070433B1SRAM supply voltage global bitline precharge pulseIBM·Filed 2014·Granted Jun 30, 2015·3 cites·20 claims
- 1263US7233542B2Method and apparatus for address generationIBM·Filed 2005·Granted Jun 19, 2007·5 cites·8 claims
- 1360US11067627B2Noise injection circuitIBM·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 1460US6728912B2SOI cell stability test methodIBM·Filed 2001·Granted Apr 27, 2004·11 cites·4 claims
- 1558US9792967B1Managing semiconductor memory array leakage currentIBM·Filed 2016·Granted Oct 17, 2017·1 cites·14 claims
- 1658US8299833B2Programmable control clock circuit including scan modeBUNCE PAUL A·Filed 2010·Granted Oct 30, 2012·2 cites·17 claims
- 1757US9786339B2Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservationIBM·Filed 2016·Granted Oct 10, 2017·1 cites·18 claims
- 1857US8345497B2Internal bypassing of memory array devicesIBM·Filed 2010·Granted Jan 1, 2013·2 cites·15 claims
- 1956US9971394B2Cache array with reduced power consumptionIBM·Filed 2014·Granted May 15, 2018·0 cites·5 claims
- 2056US9281024B2Write/read priority blocking scheme using parallel static address decode pathIBM·Filed 2014·Granted Mar 8, 2016·1 cites·8 claims
- 2156US7688650B2Write control method for a memory array configured with multiple memory subarraysIBM·Filed 2008·Granted Mar 30, 2010·2 cites·5 claims
- 2255US7102944B1Programmable analog control of a bitline evaluation circuitIBM·Filed 2005·Granted Sep 5, 2006·3 cites·1 claims
- 2353US10312915B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 4, 2019·0 cites·20 claims
- 2453US10312916B2Dynamic decode circuit with delayed prechargeIBM·Filed 2018·Granted Jun 4, 2019·0 cites·15 claims
- 2553US7299374B2Clock control method and apparatus for a memory arrayIBM·Filed 2005·Granted Nov 20, 2007·2 cites·20 claims
- 2652US10320388B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 11, 2019·0 cites·19 claims
- 2752US7023759B1System and method for synchronizing memory array signalsIBM·Filed 2005·Granted Apr 4, 2006·2 cites·19 claims
- 2851US10224933B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted Mar 5, 2019·0 cites·16 claims
- 2951US9977485B2Cache array with reduced power consumptionIBM·Filed 2012·Granted May 22, 2018·0 cites·4 claims
- 3051US2008028255A1Clock control method and apparatus for a memory arrayIBM·Filed 2007·Application pending·0 cites
- 3150US6584023B1System for implementing a column redundancy scheme for arrays with controls that span multiple data bitsIBM·Filed 2002·Granted Jun 24, 2003·6 cites·9 claims
- 3249US7009895B2Method for skip over redundancy decode with very low overheadIBM·Filed 2004·Granted Mar 7, 2006·5 cites·10 claims
- 3345US9281025B2Write/read priority blocking scheme using parallel static address decode pathIBM·Filed 2014·Granted Mar 8, 2016·0 cites·8 claims
- 3445US7210084B2Integrated system logic and ABIST data compression for an SRAM directoryIBM·Filed 2003·Granted Apr 24, 2007·4 cites·5 claims
- 3544US9997218B2Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservationIBM·Filed 2017·Granted Jun 12, 2018·0 cites·1 claims
- 3643US9761289B1Managing semiconductor memory array leakage currentIBM·Filed 2016·Granted Sep 12, 2017·0 cites·6 claims
- 3743US6822885B2High speed latch and compare functionIBM·Filed 2003·Granted Nov 23, 2004·3 cites·12 claims
- 3843US2006179382A1Method and circuit for implementing array bypass operations without access penaltyIBM·Filed 2005·Application pending·0 cites
- 3942US11150818B2Memory array having power consumption characteristicsIBM·Filed 2019·Granted Oct 19, 2021·0 cites·19 claims
- 4042US10978140B2Random-access memory array memory cell selectionIBM·Filed 2019·Granted Apr 13, 2021·0 cites·14 claims
- 4142US10840895B1Fine-grained programmable delay and pulse shaping circuitIBM·Filed 2019·Granted Nov 17, 2020·0 cites·9 claims
- 4239US8861284B2Increasing memory operating frequencyIBM·Filed 2012·Granted Oct 14, 2014·0 cites·19 claims
- 4337US7266737B2Method for enabling scan of defective ram prior to repairIBM·Filed 2005·Granted Sep 4, 2007·0 cites·19 claims
- 4436US9583211B1Incorporating bit write capability with column interleave write enable and column redundancy steeringIBM·Filed 2016·Granted Feb 28, 2017·0 cites·20 claims
- 4536US9355692B2High frequency write through memory deviceIBM·Filed 2012·Granted May 31, 2016·0 cites·3 claims
- 4636US8351278B2Jam latch for latching memory array output dataIBM·Filed 2010·Granted Jan 8, 2013·0 cites·17 claims
- 4735US7099203B1Circuit and method for writing a binary value to a memory cellIBM·Filed 2005·Granted Aug 29, 2006·0 cites·15 claims
- 4834US2006176073A1Clocked preconditioning of intermediate nodesIBM·Filed 2005·Application pending·0 cites
- 4934US2006176747A1Circuit for interfacing local bitlines with global bitlineIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →