Inventor · disambiguated record
Paul Campbell
Also filed as: CAMPBELL PAUL · CAMPBELL PAUL W · CAMPBELL PAUL WILLIAM
21 granted patents·1 pending application·967 citations·filing 1994–2024
96Inventor score
Top patents by PatentIndex Score
22 records- 0199US7047394B1Computer for execution of RISC and CISC instruction setsATI INT SRL·Filed 2000·Granted May 16, 2006·318 cites·72 claims
- 0298US7661107B1Method and apparatus for dynamic allocation of processing resourcesADVANCED MICRO DEVICES INC·Filed 2000·Granted Feb 9, 2010·195 cites·13 claims
- 0395US6934832B1Exception mechanism for a computerATI INT SRL·Filed 2000·Granted Aug 23, 2005·152 cites·71 claims
- 0490US7228404B1Managing instruction side-effectsATI INT SRL·Filed 2000·Granted Jun 5, 2007·66 cites·52 claims
- 0585US6249288B1Multi thread display controllerATI INT SRL·Filed 1998·Granted Jun 19, 2001·74 cites·10 claims
- 0682US10611566B1Side loading garbage truck with full eject mechanismCAMPBELL PAUL·Filed 2016·Granted Apr 7, 2020·5 cites·2 claims
- 0775US6393522B1Method and apparatus for cache memory managementATI INT SRL·Filed 2000·Granted May 21, 2002·18 cites·11 claims
- 0870US8381223B2Method and apparatus for dynamic allocation of processing resourcesVAN DYKE KORBIN·Filed 2011·Granted Feb 19, 2013·3 cites·18 claims
- 0964US7987465B2Method and apparatus for dynamic allocation of processing resourcesADVANCED MICRO DEVICES INC·Filed 2010·Granted Jul 26, 2011·1 cites·10 claims
- 1062US6571315B2Method and apparatus for cache memory managementATI INTERNAT·Filed 2001·Granted May 27, 2003·8 cites·25 claims
- 1162US5664154AM/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location's dirty bit indicates a write-backCHROMATIC RES INC·Filed 1995·Granted Sep 2, 1997·42 cites·6 claims
- 1253US2025377992A1Boot survivability for graphics processing unitINTEL CORP·Filed 2024·Application pending·0 cites
- 1343US6886090B1Method and apparatus for virtual address translationATI INT SRL·Filed 1999·Granted Apr 26, 2005·15 cites·14 claims
- 1442US5486844AMethod and apparatus for superimposing displayed imagesRADIUS INC·Filed 1994·Granted Jan 23, 1996·10 cites·2 claims
- 1539US6526459B1Allocation of input/output bus address space to native input/output devicesATI INT SRL·Filed 1999·Granted Feb 25, 2003·11 cites·9 claims
- 1638US6452599B1Method and apparatus for generating a specific computer hardware component exception handlerATI INT SRL·Filed 1999·Granted Sep 17, 2002·8 cites·24 claims
- 1737US6332184B1Method and apparatus for modifying memory accesses utilizing TLB entriesATI INT SRL·Filed 1999·Granted Dec 18, 2001·9 cites·22 claims
- 1837US6324635B1Method and apparatus for address paging emulationATI INT SRL·Filed 1999·Granted Nov 27, 2001·9 cites·19 claims
- 1936US6385712B1Method and apparatus for segregation of virtual address spaceATI INT SRL·Filed 1999·Granted May 7, 2002·8 cites·23 claims
- 2035US6418524B1Method and apparatus for dependent segmentation and paging processingATI INT SRL·Filed 1999·Granted Jul 9, 2002·6 cites·16 claims
- 2133US6301648B1Method and apparatus for processing memory accesses utilizing a TLBATI INT SRL·Filed 1999·Granted Oct 9, 2001·5 cites·27 claims
- 2232US6594750B1Method and apparatus for handling an accessed bit in a page table entryATI INT SRL·Filed 1999·Granted Jul 15, 2003·4 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →