Inventor · disambiguated record
Patrick Heyne
Also filed as: HEYNE PATRICK
39 granted patents·3 pending applications·422 citations·filing 1998–2007
98Inventor score
Top patents by PatentIndex Score
42 records- 0192US7414445B2Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signalQIMONDA AG·Filed 2006·Granted Aug 19, 2008·29 cites·22 claims
- 0289US6573754B2Circuit configuration for enabling a clock signal in a manner dependent on an enable signalINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 3, 2003·42 cites·6 claims
- 0383US7404018B2Read latency control circuitINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jul 22, 2008·15 cites·25 claims
- 0480US6661265B2Delay locked loop for generating complementary clock signalsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Dec 9, 2003·23 cites·6 claims
- 0577US6351167B1Integrated circuit with a phase locked loopSIEMENS AG·Filed 2000·Granted Feb 26, 2002·24 cites·8 claims
- 0676US6259652B1Synchronous integrated memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 10, 2001·24 cites·3 claims
- 0771US7363561B2Method and circuit arrangement for resetting an integrated circuitINFINEON TECHNOLOGIES AG·Filed 2005·Granted Apr 22, 2008·5 cites·14 claims
- 0870US6472921B1Delivering a fine delay stage for a delay locked loopSIEMENS AG·Filed 2001·Granted Oct 29, 2002·15 cites·22 claims
- 0970US6194928B1Integrated circuit with adjustable delay unitSIEMENS AG·Filed 1999·Granted Feb 27, 2001·24 cites·4 claims
- 1068US6737901B2Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay deviceINFINEON TECHNOLOGIES AG·Filed 2002·Granted May 18, 2004·13 cites·14 claims
- 1165US7304515B2Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization processINFINEON TECHNOLOGIES AG·Filed 2005·Granted Dec 4, 2007·6 cites·15 claims
- 1265US6584021B2Semiconductor memory having a delay locked loopINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 24, 2003·17 cites·7 claims
- 1364US7391245B2Delay locked loop and method for setting a delay chainINFINEON TECHNOLOGIES AG·Filed 2006·Granted Jun 24, 2008·4 cites·29 claims
- 1463US7016452B2Delay locked loopINFINEON TECHNOLOGIES AG·Filed 2002·Granted Mar 21, 2006·13 cites·7 claims
- 1563US6388944B2Memory component with short access timeINFINEON TECHNOLOGIES AG·Filed 2001·Granted May 14, 2002·13 cites·13 claims
- 1663US6285176B1Voltage generator with superimposed reference voltage and deactivation signalsINFINEON TECHNOLOGIES·Filed 2000·Granted Sep 4, 2001·13 cites·7 claims
- 1761US6285228B1Integrated circuit for generating a phase-shifted output clock signal from a clock signalINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 4, 2001·12 cites·7 claims
- 1860US6670802B2Integrated circuit having a test operating mode and method for testing a multiplicity of such circuitsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Dec 30, 2003·12 cites·7 claims
- 1959US6967893B2Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memoryINFINEON TECNOLOGIES AG·Filed 2003·Granted Nov 22, 2005·11 cites·8 claims
- 2058US6307416B1Integrated circuit for producing two output clock signals at levels which do not overlap in timeINFINEON TECHNOLOGIES AG·Filed 2000·Granted Oct 23, 2001·9 cites·7 claims
- 2154US6806752B2Method and logic/memory module for correcting the duty cycle of at least one control/reference signalINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 19, 2004·6 cites·36 claims
- 2253US6469563B2Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signalsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Oct 22, 2002·6 cites·5 claims
- 2352US6480024B2Circuit configuration for programming a delay in a signal pathINFINEON TECHNOLOGIES AG·Filed 2001·Granted Nov 12, 2002·6 cites·8 claims
- 2452US6366527B2Circuit configuration for generating an output clock signal with optimized signal generation timeINFINEON TECHNOLOGIES AG·Filed 2001·Granted Apr 2, 2002·7 cites·5 claims
- 2551US7629820B2Delay circuitQIMONDA AG·Filed 2007·Granted Dec 8, 2009·3 cites·13 claims
- 2651US6532188B2Integrated memory having a row access controller for activating and deactivating row linesINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 11, 2003·7 cites·4 claims
- 2750US6191985B1Dynamic memory having two modes of operationINFINEON TECHNOLOGIES AG·Filed 2000·Granted Feb 20, 2001·7 cites·7 claims
- 2849US6756820B1Optimized-delay multiplexerSIEMENS AG·Filed 1999·Granted Jun 29, 2004·10 cites·4 claims
- 2946US6198328B1Circuit configuration for producing complementary signalsSIEMENS AG·Filed 1999·Granted Mar 6, 2001·9 cites·3 claims
- 3044US7457392B2Delay locked loopINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 25, 2008·3 cites·9 claims
- 3142US6191627B1Integrated circuit having adjustable delay units for clock signalsSIEMENS AG·Filed 1999·Granted Feb 20, 2001·9 cites·7 claims
- 3242US6125066ACircuit configuration and method for automatic recognition and elimination of word line/bit line short circuitsINFINEON TECHNOLOGIES AG·Filed 1999·Granted Sep 26, 2000·8 cites·5 claims
- 3342US2006214709A1Circuit arrangement for generating a synchronization signalNYGREN AARON·Filed 2006·Application pending·0 cites
- 3439US6657422B2Current mirror circuitINFINEON TECHNOLOGIES AG·Filed 2001·Granted Dec 2, 2003·2 cites·10 claims
- 3538US6060908ADatabusSIEMENS AG·Filed 1998·Granted May 9, 2000·11 cites·6 claims
- 3638US2007285139A1Amplifier Circuit and Method for Correcting the Duty Ratio of a Differential Clock SignalQIMONDA AG·Filed 2007·Application pending·0 cites
- 3738US2007273416A1Signal delay loop and method for locking a signal delay loopHEYNE PATRICK·Filed 2007·Application pending·0 cites
- 3836US6928025B1Synchronous integrated memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 9, 2005·1 cites·5 claims
- 3934US6784650B2Circuit configuration for generating a controllable output voltageINFINEON TECHNOLOGIES AG·Filed 2003·Granted Aug 31, 2004·0 cites·10 claims
- 4033US7126401B2Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay deviceINFINEON TECHNOLOGIES AG·Filed 2005·Granted Oct 24, 2006·0 cites·35 claims
- 4133US6529028B1Configuration for testing a plurality of memory chips on a waferINFINEON TECHNOLOGIES AG·Filed 1999·Granted Mar 4, 2003·3 cites·4 claims
- 4232US6542389B2Voltage pump with switch-on controlINFINEON TECHNOLOGIES AG·Filed 2001·Granted Apr 1, 2003·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →