Inventor · disambiguated record
Palkesh Jain
Also filed as: JAIN PALKESH
22 granted patents·12 pending applications·99 citations·filing 2006–2024
94Inventor score
Top patents by PatentIndex Score
34 records- 0195US9628089B1Supply voltage tracking clock generator in adaptive clock distribution systemsQUALCOMM INC·Filed 2016·Granted Apr 18, 2017·23 cites·27 claims
- 0293US9897651B2Ultra-fast autonomous clock monitoring circuit for safe and secure automotive applicationsQUALCOMM INC·Filed 2016·Granted Feb 20, 2018·8 cites·18 claims
- 0385US11424621B2Configurable redundant systems for safety critical applicationsQUALCOMM INC·Filed 2020·Granted Aug 23, 2022·2 cites·30 claims
- 0485US10089194B2System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systemsQUALCOMM INC·Filed 2016·Granted Oct 2, 2018·5 cites·23 claims
- 0583US7689377B2Technique for aging induced performance drift compensation in an integrated circuitTEXAS INSTRUMENTS INC·Filed 2006·Granted Mar 30, 2010·11 cites·24 claims
- 0681US8786307B2Bias temperature instability-resistant circuitsJAIN PALKESH·Filed 2012·Granted Jul 22, 2014·6 cites·16 claims
- 0780US9665680B2Cell-level signal electromigrationUNIV MINNESOTA·Filed 2014·Granted May 30, 2017·7 cites·19 claims
- 0878US8013635B2Multi-mode circuit and a method for preventing degradation in the multi-mode circuitTEXAS INSTRUMENTS INC·Filed 2010·Granted Sep 6, 2011·6 cites·17 claims
- 0977US8219953B2Budgeting electromigration-related reliability among metal paths in the design of a circuitJAIN PALKESH·Filed 2009·Granted Jul 10, 2012·9 cites·2 claims
- 1075US10389379B2Error correcting code testingQUALCOMM INC·Filed 2017·Granted Aug 20, 2019·2 cites·30 claims
- 1175US7752582B2Method and apparatus for determining electro-migration in integrated circuit designsTEXAS INSTRUMENTS INC·Filed 2007·Granted Jul 6, 2010·9 cites·19 claims
- 1274US10901020B2Digital duty-cycle monitoring of a periodic signalQUALCOMM INC·Filed 2018·Granted Jan 26, 2021·3 cites·26 claims
- 1367US8255850B2Fabricating IC with NBTI path delay within timing constraintsJAIN PALKESH·Filed 2009·Granted Aug 28, 2012·5 cites·2 claims
- 1466US10591965B2System and method for context-aware thermal management and workload scheduling in a portable computing deviceQUALCOMM INC·Filed 2017·Granted Mar 17, 2020·1 cites·30 claims
- 1561US9915968B2Systems and methods for adaptive clock designQUALCOMM INC·Filed 2016·Granted Mar 13, 2018·1 cites·28 claims
- 1652US2025110174A1Apparatus and methods for thermal testing within electronic component assembliesQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1752US2025336767A1Liquid cooling of an integrated circuitQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1851US8296701B2Method for designing a semiconductor device based on leakage current estimationJAIN PALKESH·Filed 2010·Granted Oct 23, 2012·1 cites·20 claims
- 1951US2014024144A1Integrated circuit die and method of makingTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 2050US10141297B1Integrated device comprising device level cells with variable sizes for heat dissipation around hotspotsQUALCOMM INC·Filed 2017·Granted Nov 27, 2018·0 cites·34 claims
- 2149US11416049B2In-field monitoring of on-chip thermal, power distribution network, and power grid reliabilityQUALCOMM INC·Filed 2020·Granted Aug 16, 2022·0 cites·30 claims
- 2248US2013161718A1Integrated circuit die and method of makingJAIN PALKESH·Filed 2012·Application pending·0 cites
- 2345US10103714B2Adjust voltage for thermal mitigationQUALCOMM INC·Filed 2016·Granted Oct 16, 2018·0 cites·24 claims
- 2444US10042405B2Adjusting source voltage based on stored informationQUALCOMM INC·Filed 2015·Granted Aug 7, 2018·0 cites·16 claims
- 2543US2020019477A1Diverse redundant processing modules for error detectionQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2642US8677303B2Electromigration compensation systemJAIN PALKESH·Filed 2010·Granted Mar 18, 2014·0 cites·3 claims
- 2741US2009187368A1Burn-In Tests To Produce Fabricated Integrated Circuits With Reduced Variations Due To Process SpreadTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 2840US2012266123A1Coherent analysis of asymmetric aging and statistical process variation in electronic circuitsJAIN PALKESH·Filed 2011·Application pending·0 cites
- 2939US2018143862A1Circuits and Methods Providing Thread Assignment for a Multi-Core ProcessorQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3039US2017308637A1Probabilistic thermal hotspot accommodationQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3138US7791926B2SEU hardening circuit and methodTEXAS INSTRUMENTS INC·Filed 2007·Granted Sep 7, 2010·0 cites·19 claims
- 3236US2013002297A1Bias temperature instability-resistant circuitsTEXAS INSTRUMENTS INC·Filed 2012·Application pending·0 cites
- 3335US2016116527A1Stochastic and topologically aware electromigration analysis methodologyQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3433US2017222430A1Short-resistant output pin circuitryQUALCOMM INC·Filed 2016·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Palkesh Jain files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →