Inventor · disambiguated record
Paul J. Jordan
Also filed as: JORDAN PAUL · JORDAN PAUL J · JORDAN PAUL JOSEPH
60 granted patents·5 pending applications·1,279 citations·filing 1995–2025
99Inventor score
Top patents by PatentIndex Score
65 records- 0196US7366829B1TLB tag parity checking without CAM readSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 29, 2008·134 cites·17 claims
- 0295US7779238B2Method and apparatus for precisely identifying effective addresses associated with hardware eventsORACLE AMERICA INC·Filed 2006·Granted Aug 17, 2010·51 cites·20 claims
- 0395US7454590B2Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor coresSUN MICROSYSTEMS INC·Filed 2005·Granted Nov 18, 2008·44 cites·17 claims
- 0494US8190864B1APIC implementation for a highly-threaded x86 processorJORDAN PAUL J·Filed 2007·Granted May 29, 2012·45 cites·21 claims
- 0592US7370243B1Precise error handling in a fine grain multithreaded multicore processorSUN MICROSYSTEMS INC·Filed 2004·Granted May 6, 2008·72 cites·19 claims
- 0692US7274706B1Methods and systems for processing network dataSYRUS ZIAI·Filed 2001·Granted Sep 25, 2007·155 cites·6 claims
- 0791US7383415B2Hardware demapping of TLBs shared by multiple threadsSUN MICROSYSTEMS INC·Filed 2005·Granted Jun 3, 2008·26 cites·20 claims
- 0890US12079124B2Non-uniform memory interleave methodSAMBANOVA SYSTEMS INC·Filed 2022·Granted Sep 3, 2024·1 cites·28 claims
- 0990US6976205B1Method and apparatus for calculating TCP and UDP checksums while preserving CPU resourcesSYRUS ZIAI·Filed 2001·Granted Dec 13, 2005·89 cites·19 claims
- 1089US12271333B2Peer-to-peer route through in a reconfigurable computing systemSAMBANOVA SYSTEMS INC·Filed 2023·Granted Apr 8, 2025·1 cites·20 claims
- 1189US12243604B1Scannable memory array and a method for scanning memorySAMBANOVA SYSTEMS INC·Filed 2024·Granted Mar 4, 2025·2 cites·22 claims
- 1289US8555038B2Processor and method providing instruction support for instructions that utilize multiple register windowsOLSON CHRISTOPHER H·Filed 2010·Granted Oct 8, 2013·14 cites·18 claims
- 1389US8301865B2System and method to manage address translation requestsGROHOSKI GREGORY F·Filed 2009·Granted Oct 30, 2012·25 cites·20 claims
- 1489US7392399B2Methods and systems for efficiently integrating a cryptographic co-processorSUN MICROSYSTEMS INC·Filed 2003·Granted Jun 24, 2008·63 cites·19 claims
- 1586US11263012B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2020·Granted Mar 1, 2022·2 cites·20 claims
- 1686US7454666B1Real-time address trace generationSUN MICROSYSTEMS INC·Filed 2005·Granted Nov 18, 2008·19 cites·20 claims
- 1785US10528351B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2017·Granted Jan 7, 2020·3 cites·20 claims
- 1884US7861063B1Delay slot handling in a processorORACLE AMERICA INC·Filed 2004·Granted Dec 28, 2010·36 cites·27 claims
- 1984US7676655B2Single bit control of threads in a multithreaded multicore processorSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 9, 2010·39 cites·20 claims
- 2081US7702887B1Performance instrumentation in a fine grain multithreaded multicore processorSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 20, 2010·32 cites·19 claims
- 2179US12277041B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2023·Granted Apr 15, 2025·0 cites·20 claims
- 2278US9710273B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2014·Granted Jul 18, 2017·3 cites·20 claims
- 2378US8438208B2Processor and method for implementing instruction support for multiplication of large operandsOLSON CHRISTOPHER H·Filed 2009·Granted May 7, 2013·8 cites·20 claims
- 2478US8412911B2System and method to invalidate obsolete address translationsGROHOSKI GREGORY F·Filed 2009·Granted Apr 2, 2013·10 cites·17 claims
- 2578US7373489B1Apparatus and method for floating-point exception prediction and recoverySUN MICROSYSTEMS INC·Filed 2004·Granted May 13, 2008·25 cites·24 claims
- 2677US7178005B1Efficient implementation of timers in a multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Feb 13, 2007·23 cites·23 claims
- 2777US6701484B1Register file with delayed parity checkIBM·Filed 2000·Granted Mar 2, 2004·24 cites·18 claims
- 2876US8099586B2Branch misprediction recovery mechanism for microprocessorsCHOU YUAN C·Filed 2008·Granted Jan 17, 2012·7 cites·17 claims
- 2976US6857083B2Method and system for triggering a debugging unitIBM·Filed 2000·Granted Feb 15, 2005·23 cites·32 claims
- 3075US12340195B2Handling interrupts from a virtual function in a system with a reconfigurable processorSAMBANOVA SYSTEMS INC·Filed 2023·Granted Jun 24, 2025·0 cites·17 claims
- 3175US8429386B2Dynamic tag allocation in a multithreaded out-of-order processorJORDAN PAUL J·Filed 2009·Granted Apr 23, 2013·7 cites·15 claims
- 3274US11709742B2Method for migrating CPU state from an inoperable core to a spare coreORACLE INT CORP·Filed 2022·Granted Jul 25, 2023·0 cites·20 claims
- 3373US9971565B2Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of coresORACLE INT CORP·Filed 2015·Granted May 15, 2018·2 cites·19 claims
- 3473US8078942B2Register error correction of speculative data in an out-of-order processorJORDAN PAUL J·Filed 2007·Granted Dec 13, 2011·5 cites·19 claims
- 3572US6785847B1Soft error detection in high speed microprocessorsIBM·Filed 2000·Granted Aug 31, 2004·16 cites·20 claims
- 3671US7543132B1Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizesSUN MICROSYSTEMS INC·Filed 2004·Granted Jun 2, 2009·17 cites·20 claims
- 3770US12147339B2Non-uniform memory interleaving processorSAMBANOVA SYSTEMS INC·Filed 2023·Granted Nov 19, 2024·0 cites·16 claims
- 3870US7430643B2Multiple contexts for efficient use of translation lookaside bufferSUN MICROSYSTEMS INC·Filed 2004·Granted Sep 30, 2008·18 cites·21 claims
- 3970US2025199985A1Peer-to-peer route through in a reconfigurable computing systemSAMBANOVA SYSTEMS INC·Filed 2025·Application pending·0 cites
- 4069US9940132B2Load-monitor mwaitORACLE INT CORP·Filed 2015·Granted Apr 10, 2018·1 cites·12 claims
- 4166US8732430B2Method and apparatus for using unused bits in a memory pointerRADOVIC ZORAN·Filed 2011·Granted May 20, 2014·2 cites·20 claims
- 4266US7350053B1Software accessible fast VA to PA translationSUN MICROSYSTEMS INC·Filed 2005·Granted Mar 25, 2008·3 cites·15 claims
- 4365US7343474B1Minimal address state in a fine grain multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 11, 2008·10 cites·30 claims
- 4465US5974524AMethod and apparatus for reducing the number of rename registers in a processor supporting out-of-order executionIBM·Filed 1997·Granted Oct 26, 1999·46 cites·22 claims
- 4565US2024412797A1Fully Scannable Memory ArraysSAMBANOVA SYSTEMS INC·Filed 2023·Application pending·0 cites
- 4664US2024412798A1Method for Scanning a Memory ArraySAMBANOVA SYSTEMS INC·Filed 2024·Application pending·0 cites
- 4761US8504805B2Processor operating mode for mitigating dependency conditions between instructions having different operand sizesGOLLA ROBERT T·Filed 2009·Granted Aug 6, 2013·2 cites·16 claims
- 4860US7937556B2Minimizing TLB comparison sizeORACLE AMERICA INC·Filed 2008·Granted May 3, 2011·1 cites·20 claims
- 4960US5805849AData processing system and method for using an unique identifier to maintain an age relationship between executing instructionsIBM·Filed 1997·Granted Sep 8, 1998·36 cites·23 claims
- 5058US9507656B2Mechanism for handling unfused multiply-accumulate accrued exception bits in a processorBROOKS JEFFREY S·Filed 2009·Granted Nov 29, 2016·1 cites·18 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Paul J. Jordan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →