Inventor · disambiguated record
Parivallal Kannan
Also filed as: KANNAN PARIVALLAL
14 granted patents·1 pending application·84 citations·filing 2005–2024
91Inventor score
Top patents by PatentIndex Score
15 records- 0193US11797280B1Balanced partitioning of neural network based on execution latenciesAMAZON TECH INC·Filed 2021·Granted Oct 24, 2023·4 cites·21 claims
- 0289US12164462B2Micro-network-on-chip and microsector infrastructureINTEL CORP·Filed 2020·Granted Dec 10, 2024·2 cites·19 claims
- 0387US12367021B1Fast interference graph construction for a binary tree of interval nodesAMAZON TECH INC·Filed 2023·Granted Jul 22, 2025·1 cites·20 claims
- 0483US10318699B1Fixing hold time violations using hold time budgets and slacks of setup timesXILINX INC·Filed 2017·Granted Jun 11, 2019·4 cites·20 claims
- 0583US7958480B1Placement of I/O blocks within I/O banks using an integer linear programming formulationXILINX INC·Filed 2008·Granted Jun 7, 2011·14 cites·20 claims
- 0681US7516437B1Skew-driven routing for networksXILINX INC·Filed 2006·Granted Apr 7, 2009·11 cites·10 claims
- 0777US8122420B1Congestion elimination using adaptive cost schedule to route signals within an integrated circuitKANNAN PARIVALLAL·Filed 2009·Granted Feb 21, 2012·10 cites·19 claims
- 0877US7480884B1Assignment of select I/O objects to banks with mixed capacities using integer linear programmingXILINX INC·Filed 2006·Granted Jan 20, 2009·10 cites·17 claims
- 0975US8196082B1Signal routing and pin placementKANNAN PARIVALLAL·Filed 2010·Granted Jun 5, 2012·5 cites·14 claims
- 1075US7353485B1Method of flexible clock placement for integrated circuit designs using integer linear programmingXILINX INC·Filed 2005·Granted Apr 1, 2008·8 cites·20 claims
- 1172US2025036591A1Micro-network-on-chip and microsector infrastructureINTEL CORP·Filed 2024·Application pending·0 cites
- 1271US10416232B1Timing optimizations in circuit designs using opposite clock edge triggered flip-flopsXILINX INC·Filed 2018·Granted Sep 17, 2019·1 cites·20 claims
- 1371US7451422B1Simultaneous assignment of select I/O objects and clock I/O objects to banks using integer linear programmingXILINX INC·Filed 2006·Granted Nov 11, 2008·6 cites·20 claims
- 1470US8010924B1Assignment of select input/output blocks to banks for integrated circuits using integer linear programming with proximity optimizationXILINX INC·Filed 2008·Granted Aug 30, 2011·5 cites·20 claims
- 1564US7530045B1Recursive partitioning based placement for programmable logic devices using non-rectilinear device-cutlinesXILINX INC·Filed 2006·Granted May 5, 2009·3 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →