Inventor · disambiguated record
Patrick Knebel
Also filed as: KNEBEL PATRICK
24 granted patents·5 pending applications·518 citations·filing 1993–2014
96Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO13HEWLETT PACKARD CO6KNEBEL PATRICK2LESARTRE GREGG B2DE DINECHIN CHRISTOPHE1
Top patents by PatentIndex Score
29 records- 0191US8683139B2Cache and method for cache bypass functionalityGAITHER BLAINE D·Filed 2006·Granted Mar 25, 2014·23 cites·9 claims
- 0284US5867644ASystem and method for on-chip debug support and performance monitoring in a microprocessorHEWLETT PACKARD CO·Filed 1996·Granted Feb 2, 1999·124 cites·30 claims
- 0381US6003107ACircuitry for providing external access to signals that are internal to an integrated circuit chip packageHEWLETT PACKARD CO·Filed 1996·Granted Dec 14, 1999·98 cites·19 claims
- 0480US6820190B1Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructionsHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 16, 2004·29 cites·4 claims
- 0577US9405696B2Cache and method for cache bypass functionalityHEWLETT PACKARD DEVELOPMENT CO LP·Filed 2014·Granted Aug 2, 2016·3 cites·11 claims
- 0676US6625759B1Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unitHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Sep 23, 2003·22 cites·18 claims
- 0775US7343479B2Method and apparatus for implementing two architectures in a chipHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 11, 2008·18 cites·13 claims
- 0873US7139936B2Method and apparatus for verifying the correctness of a processor behavioral modelHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Nov 21, 2006·16 cites·18 claims
- 0972US6643800B1Method and apparatus for testing microarchitectural features by using tests written in microcodeHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 4, 2003·18 cites·6 claims
- 1068US8176255B2Allocating space in dedicated cache waysKNEBEL PATRICK·Filed 2007·Granted May 8, 2012·6 cites·16 claims
- 1168US5412787ATwo-level TLB having the second level TLB implemented in cache tag RAMsHEWLETT PACKARD CO·Filed 1993·Granted May 2, 1995·61 cites·13 claims
- 1267US6745322B1Apparatus and method for conditionally flushing a pipeline upon a failure of a test conditionHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Jun 1, 2004·12 cites·18 claims
- 1365US6618801B1Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template informationHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Sep 9, 2003·10 cites·20 claims
- 1464US6542862B1Determining register dependency in multiple architecture systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 1, 2003·10 cites·19 claims
- 1560US8505020B2Computer workload migration using processor poolingDE DINECHIN CHRISTOPHE·Filed 2010·Granted Aug 6, 2013·1 cites·14 claims
- 1659US6807625B1Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructionsHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Oct 19, 2004·7 cites·21 claims
- 1758US7941610B2Coherency directory updating in a multiprocessor computing systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted May 10, 2011·2 cites·24 claims
- 1852US6681322B1Method and apparatus for emulating an instruction set extension in a digital computer systemHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Jan 20, 2004·24 cites·18 claims
- 1949US7600079B2Performing a memory write of a data unit without changing ownership of the data unitHEWLETT PACKARD DEVELOPMENT CO·Filed 2006·Granted Oct 6, 2009·0 cites·14 claims
- 2046US2004068641A1Method and apparatus for exchanging the contents of registersFiled 2003·Application pending·0 cites
- 2142US2004064267A1Method and apparatus for testing microarchitectural features by using tests written in microcodeFiled 2003·Application pending·0 cites
- 2241US5860096AMulti-level instruction cache for a computerHEWLETT PACKARD CO·Filed 1996·Granted Jan 12, 1999·15 cites·6 claims
- 2341US2015113245A1Address translation gasketLESARTRE GREGG B·Filed 2012·Application pending·0 cites
- 2441US2009106496A1Updating cache bits using hint transaction signalsKNEBEL PATRICK·Filed 2007·Application pending·0 cites
- 2541US2015039873A1Processor providing multiple system imagesLESARTRE GREGG B·Filed 2012·Application pending·0 cites
- 2639US8103837B2Servicing memory read requestsLOVELL MATTHEW B·Filed 2008·Granted Jan 24, 2012·0 cites·15 claims
- 2735US5526500ASystem for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructionsHEWLETT PACKARD CO·Filed 1995·Granted Jun 11, 1996·12 cites·29 claims
- 2830US6668315B1Methods and apparatus for exchanging the contents of registersHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Dec 23, 2003·1 cites·14 claims
- 2930US5829049ASimultaneous execution of two memory reference instructions with only one address calculationHEWLETT PACKARD CO·Filed 1997·Granted Oct 27, 1998·6 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →