Inventor · disambiguated record
Pak-Kin Mak
Also filed as: MAK PAK-KIN
82 granted patents·7 pending applications·1,393 citations·filing 1991–2019
99Inventor score
Top patents by PatentIndex Score
89 records- 0196US7111130B2Coherency management for a “switchless” distributed shared memory computer systemIBM·Filed 2006·Granted Sep 19, 2006·85 cites·5 claims
- 0295US8656228B2Memory error isolation and recovery in a multiprocessor computer systemCHECK MARK A·Filed 2010·Granted Feb 18, 2014·69 cites·25 claims
- 0392US9720833B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2015·Granted Aug 1, 2017·8 cites·9 claims
- 0491US6038651ASMP clusters with remote resource managers for distributing work to other clusters while reducing bus traffic to a minimumIBM·Filed 1998·Granted Mar 14, 2000·188 cites·20 claims
- 0590US6738870B2High speed remote storage controllerIBM·Filed 2000·Granted May 18, 2004·68 cites·4 claims
- 0689US9892043B2Nested cache coherency protocol in a tiered multi-node computer systemIBM·Filed 2017·Granted Feb 13, 2018·5 cites·17 claims
- 0789US6738872B2Clustered computer system with deadlock avoidanceIBM·Filed 2000·Granted May 18, 2004·59 cites·5 claims
- 0888US10055355B1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Aug 21, 2018·4 cites·1 claims
- 0987US10339064B2Hot cache line arbitrationIBM·Filed 2017·Granted Jul 2, 2019·5 cites·20 claims
- 1087US7577795B2Disowning cache entries on aging out of the entryIBM·Filed 2006·Granted Aug 18, 2009·17 cites·3 claims
- 1186US8423736B2Maintaining cache coherence in a multi-node, symmetric multiprocessing computerBLAKE MICHAEL A·Filed 2010·Granted Apr 16, 2013·10 cites·18 claims
- 1285US6988173B2Bus protocol for a switchless distributed shared memory computer systemIBM·Filed 2003·Granted Jan 17, 2006·49 cites·22 claims
- 1385US6738871B2Method for deadlock avoidance in a cluster environmentIBM·Filed 2000·Granted May 18, 2004·42 cites·6 claims
- 1485US6516393B1Dynamic serialization of memory access in a multi-processor systemIBM·Filed 2000·Granted Feb 4, 2003·43 cites·4 claims
- 1585US5752264AComputer architecture incorporating processor clusters and hierarchical cache memoriesIBM·Filed 1996·Granted May 12, 1998·135 cites·26 claims
- 1684US10310982B2Target cache line arbitration within a processor clusterIBM·Filed 2016·Granted Jun 4, 2019·4 cites·20 claims
- 1784US6654925B1Method to determine retries for parallel ECC correction in a pipelineIBM·Filed 2000·Granted Nov 25, 2003·37 cites·9 claims
- 1883US10628313B2Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cacheIBM·Filed 2017·Granted Apr 21, 2020·3 cites·8 claims
- 1983US9244851B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexIBM·Filed 2013·Granted Jan 26, 2016·6 cites·6 claims
- 2082US10489294B2Hot cache line fairness arbitration in distributed modular SMP systemIBM·Filed 2017·Granted Nov 26, 2019·3 cites·18 claims
- 2182US8918587B2Multilevel cache hierarchy for finding a cache line on a remote nodeBRONSON TIMOTHY C·Filed 2012·Granted Dec 23, 2014·6 cites·13 claims
- 2282US7085897B2Memory management for a symmetric multiprocessor computer systemIBM·Filed 2003·Granted Aug 1, 2006·34 cites·22 claims
- 2381US7590899B2Processor memory array having memory macros for relocatable store protect keysIBM·Filed 2006·Granted Sep 15, 2009·12 cites·18 claims
- 2481US6119219ASystem serialization with early release of individual processorIBM·Filed 1998·Granted Sep 12, 2000·98 cites·13 claims
- 2580US10572385B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2017·Granted Feb 25, 2020·2 cites·20 claims
- 2680US9858190B2Maintaining order with parallel access data streamsIBM·Filed 2015·Granted Jan 2, 2018·3 cites·12 claims
- 2780US9594689B2Designated cache data backup during system operationIBM·Filed 2015·Granted Mar 14, 2017·3 cites·17 claims
- 2879US10628314B2Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cacheIBM·Filed 2017·Granted Apr 21, 2020·2 cites·6 claims
- 2978US10649908B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Granted May 12, 2020·1 cites·17 claims
- 3078US7475193B2Separate data and coherency cache directories in a shared cache in a multiprocessor systemIBM·Filed 2006·Granted Jan 6, 2009·9 cites·19 claims
- 3177US7085898B2Coherency management for a “switchless” distributed shared memory computer systemIBM·Filed 2003·Granted Aug 1, 2006·21 cites·22 claims
- 3276US6079013AMultiprocessor serialization with early release of processorsIBM·Filed 1998·Granted Jun 20, 2000·76 cites·11 claims
- 3375US10437729B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Oct 8, 2019·1 cites·12 claims
- 3475US9348524B1Memory controlled operations under dynamic relocation of storageIBM·Filed 2014·Granted May 24, 2016·3 cites·20 claims
- 3575US9003127B2Storing data in a system memory for a subsequent cache flushIBM·Filed 2013·Granted Apr 7, 2015·3 cites·9 claims
- 3675US5490261AInterlock for controlling processor ownership of pipelined data for a store in cacheIBM·Filed 1991·Granted Feb 6, 1996·81 cites·12 claims
- 3774US8762651B2Maintaining cache coherence in a multi-node, symmetric multiprocessing computerBLAKE MICHAEL A·Filed 2010·Granted Jun 24, 2014·4 cites·17 claims
- 3873US8898503B2Low latency data transfer between clock domains operated in various synchronization modesIBM·Filed 2013·Granted Nov 25, 2014·3 cites·20 claims
- 3973US7934059B2Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetchingIBM·Filed 2008·Granted Apr 26, 2011·6 cites·20 claims
- 4072US9852071B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2014·Granted Dec 26, 2017·2 cites·20 claims
- 4171US9292445B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2014·Granted Mar 22, 2016·2 cites·11 claims
- 4270US9323676B2Non-data inclusive coherent (NIC) directory for cacheIBM·Filed 2013·Granted Apr 26, 2016·2 cites·8 claims
- 4369US8250308B2Cache coherency protocol with built in avoidance for conflicting responsesPAPAZOVA VESSELINA K·Filed 2008·Granted Aug 21, 2012·7 cites·19 claims
- 4468US9798663B2Granting exclusive cache access using locality cache coherency stateIBM·Filed 2015·Granted Oct 24, 2017·1 cites·10 claims
- 4568US9003125B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexAMBROLADZE EKATERINA M·Filed 2012·Granted Apr 7, 2015·2 cites·11 claims
- 4668US8560776B2Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing systemDRAPALA GARRETT M·Filed 2008·Granted Oct 15, 2013·4 cites·20 claims
- 4768US7890704B2Implementing an enhanced hover state with active prefetchesIBM·Filed 2006·Granted Feb 15, 2011·4 cites·14 claims
- 4868US5564062AResource arbitration system with resource checking and lockout avoidanceIBM·Filed 1995·Granted Oct 8, 1996·53 cites·9 claims
- 4966US9600361B2Dynamic partial blocking of a cache ECC bypassIBM·Filed 2015·Granted Mar 21, 2017·1 cites·6 claims
- 5066US8131945B2Disowning cache entries on aging out of the entryHUTTON DAVID S·Filed 2009·Granted Mar 6, 2012·3 cites·30 claims
Showing the top 50 of 89 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →