Inventor · disambiguated record
Paul Gilbert Meyer
Also filed as: MEYER PAUL · MEYER PAUL G · MEYER PAUL GILBERT
38 granted patents·3 pending applications·128 citations·filing 1996–2023
96Inventor score
Files withAMAZON TECH INC22ADVANCED RISC MACH LTD13INTEL CORP2ANALOG DEVICES INC1MCDONALD ROBERT GREGORY1
Top patents by PatentIndex Score
41 records- 0197US11803736B1Fine-grained sparsity computations in systolic arrayAMAZON TECH INC·Filed 2020·Granted Oct 31, 2023·20 cites·19 claims
- 0297US11435941B1Matrix transpose hardware accelerationAMAZON TECH INC·Filed 2020·Granted Sep 6, 2022·14 cites·20 claims
- 0396US11500962B1Emulating fine-grained sparsity in a systolic arrayAMAZON TECH INC·Filed 2020·Granted Nov 15, 2022·10 cites·20 claims
- 0495US11880682B2Systolic array with efficient input reduction and extended array performanceAMAZON TECH INC·Filed 2021·Granted Jan 23, 2024·5 cites·21 claims
- 0594US11625453B1Using shared data bus to support systolic array tilingAMAZON TECH INC·Filed 2019·Granted Apr 11, 2023·12 cites·24 claims
- 0693US12182695B1Fine-grained sparsity computations in systolic arrayAMAZON TECH INC·Filed 2023·Granted Dec 31, 2024·2 cites·20 claims
- 0793US12039330B1Programmable vector engine for efficient beam searchAMAZON TECH INC·Filed 2021·Granted Jul 16, 2024·3 cites·20 claims
- 0890US12045475B1Resizable scratchpad memoryAMAZON TECH INC·Filed 2021·Granted Jul 23, 2024·2 cites·21 claims
- 0990US12008368B2Programmable compute engine having transpose operationsAMAZON TECH INC·Filed 2022·Granted Jun 11, 2024·2 cites·20 claims
- 1089US11941397B1Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processorAMAZON TECH INC·Filed 2022·Granted Mar 26, 2024·3 cites·20 claims
- 1189US10698825B1Inter-chip communication in a multi-chip systemADVANCED RISC MACH LTD·Filed 2019·Granted Jun 30, 2020·7 cites·17 claims
- 1288US12130885B1Emulating fine-grained sparsity in a systolic arrayAMAZON TECH INC·Filed 2022·Granted Oct 29, 2024·1 cites·20 claims
- 1387US12260214B1Throughput increase for compute engineAMAZON TECH INC·Filed 2022·Granted Mar 25, 2025·2 cites·21 claims
- 1487US12242853B1Configurable vector compute engineAMAZON TECH INC·Filed 2022·Granted Mar 4, 2025·1 cites·20 claims
- 1585US9891976B2Error detection circuitry for use with memoryADVANCED RISC MACH LTD·Filed 2015·Granted Feb 13, 2018·5 cites·11 claims
- 1683US12423058B2Systolic array with input reduction to multiple reduced inputsAMAZON TECH INC·Filed 2021·Granted Sep 23, 2025·1 cites·20 claims
- 1783US10402349B2Memory controller having data access hint message for specifying the given range of one or more memory addressesADVANCED RISC MACH LTD·Filed 2017·Granted Sep 3, 2019·3 cites·26 claims
- 1881US10324858B2Access controlADVANCED RISC MACH LTD·Filed 2017·Granted Jun 18, 2019·3 cites·16 claims
- 1978US12380321B1Flexible array data loadingAMAZON TECH INC·Filed 2019·Granted Aug 5, 2025·2 cites·20 claims
- 2076US10761987B2Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operationADVANCED RISC MACH LTD·Filed 2018·Granted Sep 1, 2020·2 cites·17 claims
- 2175US8725953B2Local cache power control within a multiprocessor systemPAVER NIGEL C·Filed 2009·Granted May 13, 2014·9 cites·21 claims
- 2271US12141468B1Matrix transpose hardware accelerationAMAZON TECH INC·Filed 2022·Granted Nov 12, 2024·0 cites·20 claims
- 2365US10095631B2System address map for hashing within a chip and between chipsADVANCED RISC MACH LTD·Filed 2015·Granted Oct 9, 2018·1 cites·16 claims
- 2461US12468507B1Reducing power consumption in integrated circuitsAMAZON TECH INC·Filed 2021·Granted Nov 11, 2025·0 cites·24 claims
- 2561US10713187B2Memory controller having data access hint message for specifying the given range of one or more memory addressesADVANCED RISC MACH LTD·Filed 2019·Granted Jul 14, 2020·0 cites·19 claims
- 2661US8977837B2Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomesMCDONALD ROBERT GREGORY·Filed 2009·Granted Mar 10, 2015·4 cites·17 claims
- 2760US7047271B2DSP execution unit for efficient alternate modes for processing multiple data sizesANALOG DEVICES INC·Filed 2004·Granted May 16, 2006·6 cites·9 claims
- 2858US12182691B1Increasing performance of computational array acceleratorsAMAZON TECH INC·Filed 2021·Granted Dec 31, 2024·0 cites·20 claims
- 2954US12271732B1Configuration of a deep vector engine using an opcode table, control table, and datapath tableAMAZON TECH INC·Filed 2022·Granted Apr 8, 2025·0 cites·20 claims
- 3054US6725360B1Selectively processing different size data in multiplier and ALU paths in parallelINTEL CORP·Filed 2000·Granted Apr 20, 2004·3 cites·10 claims
- 3152US8255629B2Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffersMEYER PAUL GILBERT·Filed 2009·Granted Aug 28, 2012·1 cites·19 claims
- 3251US12099840B1Throughput increase for tensor operationsAMAZON TECH INC·Filed 2023·Granted Sep 24, 2024·0 cites·21 claims
- 3349US11256623B2Cache content managementADVANCED RISC MACH LTD·Filed 2017·Granted Feb 22, 2022·0 cites·21 claims
- 3449US2023100930A1Mixing sparsity compressionAMAZON TECH INC·Filed 2021·Application pending·0 cites
- 3549US2024103813A1Compute engine with transpose circuitryAMAZON TECH INC·Filed 2022·Application pending·0 cites
- 3647US10783080B2Cache maintenance operations in a data processing systemADVANCED RISC MACH LTD·Filed 2018·Granted Sep 22, 2020·0 cites·20 claims
- 3747US2010217937A1Data processing apparatus and methodADVANCED RISC MACH LTD·Filed 2009·Application pending·0 cites
- 3844US11314648B2Data processingADVANCED RISC MACH LTD·Filed 2017·Granted Apr 26, 2022·0 cites·17 claims
- 3943US10591977B2Segregated power state control in a distributed cache systemADVANCED RISC MACH LTD·Filed 2015·Granted Mar 17, 2020·0 cites·19 claims
- 4040US10423466B2Optimized streaming in an un-ordered interconnectADVANCED RISC MACH LTD·Filed 2016·Granted Sep 24, 2019·0 cites·18 claims
- 4130US5889975AMethod and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor coreINTEL CORP·Filed 1996·Granted Mar 30, 1999·4 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →