Inventor · disambiguated record
Parag Parikh
Also filed as: PARIKH PARAG · PARIKH PARAG D
11 granted patents·179 citations·filing 2003–2006
90Inventor score
Files withAGERE SYSTEMS INC11
Top patents by PatentIndex Score
11 records- 0192US7042258B2Signal generator with selectable mode controlAGERE SYSTEMS INC·Filed 2004·Granted May 9, 2006·66 cites·24 claims
- 0288US7737665B2Multi-threshold charging of a rechargeable batteryAGERE SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·38 cites·17 claims
- 0385US7612592B2Programmable duty-cycle generatorAGERE SYSTEMS INC·Filed 2005·Granted Nov 3, 2009·16 cites·22 claims
- 0480US6919744B2Spectrum profile control for a PLL and the likeAGERE SYSTEMS INC·Filed 2003·Granted Jul 19, 2005·27 cites·20 claims
- 0569US7830101B2Regulation of electrical current through a resistive loadAGERE SYSTEMS INC·Filed 2006·Granted Nov 9, 2010·4 cites·25 claims
- 0662US7061331B2Clock generation circuits providing slewing of clock frequencyAGERE SYSTEMS INC·Filed 2004·Granted Jun 13, 2006·13 cites·31 claims
- 0756US7685454B2Signal buffering and retiming circuit for multiple memoriesAGERE SYSTEMS INC·Filed 2006·Granted Mar 23, 2010·4 cites·20 claims
- 0851US7434082B2Multi-stage clock selectorAGERE SYSTEMS INC·Filed 2005·Granted Oct 7, 2008·2 cites·50 claims
- 0946US7352837B2Digital phase-locked loopAGERE SYSTEMS INC·Filed 2004·Granted Apr 1, 2008·4 cites·21 claims
- 1045US7123064B2Digital phase shift circuitsAGERE SYSTEMS INC·Filed 2004·Granted Oct 17, 2006·4 cites·33 claims
- 1138US7593831B2Method and apparatus for testing delay linesAGERE SYSTEMS INC·Filed 2006·Granted Sep 22, 2009·1 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →