Inventor · disambiguated record
Paul J. Smith
Also filed as: SMITH PAUL · SMITH PAUL J · SMITH PAUL JEFFREY
11 granted patents·312 citations·filing 1997–2012
91Inventor score
Top patents by PatentIndex Score
11 records- 0188US6446248B1Spare cells placement methodologyLSI LOGIC CORP·Filed 2000·Granted Sep 3, 2002·52 cites·21 claims
- 0279US6560716B1System for measuring delay of digital signal using clock generator and delay unit wherein a set of digital elements of clock generator identical to a set of digital elements of delay unitLSI LOGIC CORP·Filed 1999·Granted May 6, 2003·106 cites·26 claims
- 0374US6459313B1IO power management: synchronously regulated output skewLSI LOGIC CORP·Filed 1998·Granted Oct 1, 2002·43 cites·20 claims
- 0471US7719368B1Configurable reset circuit for a phase-locked loopAGERE SYSTEMS INC·Filed 2008·Granted May 18, 2010·11 cites·21 claims
- 0568US6647027B1Method and apparatus for multi-channel data delay equalizationLSI LOGIC CORP·Filed 1999·Granted Nov 11, 2003·62 cites·66 claims
- 0667US8745457B2Methods and structure for utilizing external interfaces used during normal operation of a circuit to output test signalsSAGHI EUGENE·Filed 2012·Granted Jun 3, 2014·2 cites·18 claims
- 0765US6292409B1System for programmable chip initializationLSI LOGIC CORP·Filed 2000·Granted Sep 18, 2001·14 cites·21 claims
- 0857US7028233B2Characteristic image of electrical data busLSI LOGIC CORP·Filed 2003·Granted Apr 11, 2006·6 cites·20 claims
- 0943US5905744ATest mode for multifunction PCI deviceLSI LOGIC CORP·Filed 1997·Granted May 18, 1999·16 cites·34 claims
- 1041US8738979B2Methods and structure for correlation of test signals routed using different signaling pathwaysSMITH PAUL J·Filed 2012·Granted May 27, 2014·0 cites·20 claims
- 1139US7617428B2Circuits and associated methods for improved debug and test of an application integrated circuitLSI CORP·Filed 2006·Granted Nov 10, 2009·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →