Inventor · disambiguated record
Peter H. Alfke
Also filed as: ALFKE PETER · ALFKE PETER H
41 granted patents·1,681 citations·filing 1975–2010
98Inventor score
Top patents by PatentIndex Score
41 records- 0196US6759869B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2002·Granted Jul 6, 2004·83 cites·24 claims
- 0295US7667500B1Glitch-suppressor circuits and methodsXILINX INC·Filed 2006·Granted Feb 23, 2010·30 cites·18 claims
- 0394US7057413B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2004·Granted Jun 6, 2006·65 cites·24 claims
- 0494US6441641B1Programmable logic device with partial battery backupXILINX INC·Filed 2000·Granted Aug 27, 2002·113 cites·6 claims
- 0593US5969543AInput signal interface with independently controllable pull-up and pull-down circuitryXILINX INC·Filed 1997·Granted Oct 19, 1999·90 cites·15 claims
- 0692US4084082AProgrammable counterFAIRCHILD CAMERA INSTR CO·Filed 1976·Granted Apr 11, 1978·36 cites·3 claims
- 0791US6810514B1Controller arrangement for partial reconfiguration of a programmable logic deviceXILINX INC·Filed 2002·Granted Oct 26, 2004·77 cites·22 claims
- 0891US6150863AUser-controlled delay circuit for a programmable logic deviceXILINX INC·Filed 1998·Granted Nov 21, 2000·73 cites·15 claims
- 0991US5600271AInput signal interface with independently controllable pull-up and pull-down circuitryXILINX INC·Filed 1995·Granted Feb 4, 1997·75 cites·20 claims
- 1091US3980951AElectronic tuning control system for televisionFAIRCHILD CAMERA INSTR CO·Filed 1975·Granted Sep 14, 1976·25 cites·10 claims
- 1190US6734703B1Circuits and methods for analyzing timing characteristics of sequential logic elementsXILINX INC·Filed 2002·Granted May 11, 2004·37 cites·18 claims
- 1289US6389490B1FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signalsXILINX INC·Filed 2000·Granted May 14, 2002·49 cites·23 claims
- 1387US6134191AOscillator for measuring on-chip delaysXILINX INC·Filed 1999·Granted Oct 17, 2000·54 cites·19 claims
- 1487US6002282AFeedback apparatus for adjusting clock delayXILINX INC·Filed 1996·Granted Dec 14, 1999·68 cites·17 claims
- 1586US7759801B1Tapered signal linesXILINX INC·Filed 2007·Granted Jul 20, 2010·12 cites·20 claims
- 1686US6934198B1First-in, first-out buffer system in an integrated circuitXILINX INC·Filed 2004·Granted Aug 23, 2005·40 cites·24 claims
- 1786US6434642B1FIFO memory system and method with improved determination of full and empty conditions and amount of data storedXILINX INC·Filed 1999·Granted Aug 13, 2002·100 cites·16 claims
- 1886US6104211ASystem for preventing radiation failures in programmable logic devicesXILINX INC·Filed 1998·Granted Aug 15, 2000·125 cites·17 claims
- 1985US6956776B1Almost full, almost empty memory systemXILINX INC·Filed 2004·Granted Oct 18, 2005·43 cites·30 claims
- 2085US6937172B1Method and system for gray-coding countingXILINX INC·Filed 2004·Granted Aug 30, 2005·41 cites·12 claims
- 2185US6204695B1Clock-gating circuit for reducing power consumptionXILINX INC·Filed 1999·Granted Mar 20, 2001·122 cites·8 claims
- 2284US7839181B1Glitch-suppressor circuits and methodsXILINX INC·Filed 2010·Granted Nov 23, 2010·6 cites·11 claims
- 2384US7161849B1First-in, first-out buffer system in an integrated circuitXILINX INC·Filed 2005·Granted Jan 9, 2007·12 cites·17 claims
- 2483US7254677B1First-in, first-out memory system with reduced cycle latencyXILINX INC·Filed 2004·Granted Aug 7, 2007·38 cites·5 claims
- 2581US4023116APhase-locked loop frequency synthesizerFAIRCHILD CAMERA INSTR CO·Filed 1976·Granted May 10, 1977·34 cites·11 claims
- 2680US7268594B1Direct digital synthesis with low jitterXILINX INC·Filed 2005·Granted Sep 11, 2007·10 cites·13 claims
- 2779US7020862B1Circuits and methods for analyzing timing characteristics of sequential logic elementsXILINX INC·Filed 2004·Granted Mar 28, 2006·18 cites·14 claims
- 2872US7574635B1Circuit for and method of testing a memory deviceXILINX INC·Filed 2004·Granted Aug 11, 2009·19 cites·22 claims
- 2971US8352526B1Direct digital synthesis with reduced jitterXILINX INC·Filed 2006·Granted Jan 8, 2013·5 cites·18 claims
- 3067US6260139B1FPGA control structure for self-reconfigurationXILINX INC·Filed 1999·Granted Jul 10, 2001·49 cites·32 claims
- 3165US7291923B1Tapered signal linesXILINX INC·Filed 2003·Granted Nov 6, 2007·10 cites·18 claims
- 3265US5898893AFifo memory system and method for controllingXILINX INC·Filed 1997·Granted Apr 27, 1999·48 cites·15 claims
- 3360US8265902B1Circuit for measuring a time interval using a high-speed serial receiverBRADY NOEL J·Filed 2009·Granted Sep 11, 2012·4 cites·17 claims
- 3460US7755381B1Reducing noise on a supply voltage in an integrated circuitXILINX INC·Filed 2009·Granted Jul 13, 2010·3 cites·18 claims
- 3560US7535789B1Circuits and methods of concatenating FIFOsXILINX INC·Filed 2006·Granted May 19, 2009·4 cites·12 claims
- 3658US4412339AZero-crossing interpolator to reduce isochronous distortion in a digital FSK modemADVANCED MICRO DEVICES INC·Filed 1981·Granted Oct 25, 1983·20 cites·8 claims
- 3751US6353341B1Method and apparatus for discriminating against signal interferenceXILINX INC·Filed 1999·Granted Mar 5, 2002·15 cites·4 claims
- 3850US7227387B1Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay valueXILINX INC·Filed 2005·Granted Jun 5, 2007·1 cites·14 claims
- 3946US5758192AFIFO memory system determining full empty using predetermined address segments and method for controlling sameXILINX INC·Filed 1995·Granted May 26, 1998·19 cites·17 claims
- 4034US6407612B1Method and system for suppressing input signal irregularitiesXILINX INC·Filed 2000·Granted Jun 18, 2002·0 cites·3 claims
- 4131US4437158ASystem bus protocol interface circuitADVANCED MICRO DEVICES INC·Filed 1981·Granted Mar 13, 1984·8 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →