Inventor · disambiguated record
Peter A. Beerel
Also filed as: BEEREL PETER · BEEREL PETER A
17 granted patents·2 pending applications·609 citations·filing 1997–2023
95Inventor score
Files withFULCRUM MICROSYSTEMS INC4INTEL CORP4UNIV SOUTHERN CALIFORNIA4BEEREL PETER A2DIMOU GEORGIOS2
Top patents by PatentIndex Score
19 records- 0194US6854096B2Optimization of cell subtypes in a hierarchical design flowFULCRUM MICROSYSTEMS INC·Filed 2003·Granted Feb 8, 2005·302 cites·34 claims
- 0293US7584449B2Logic synthesis of multi-level domino asynchronous pipelinesFULCRUM MICROSYSTEMS INC·Filed 2005·Granted Sep 1, 2009·35 cites·27 claims
- 0391US8051396B2Logic synthesis of multi-level domino asynchronous pipelinesFULCRUM MICROSYSTEMS INC·Filed 2009·Granted Nov 1, 2011·27 cites·20 claims
- 0483US9558309B2Timing violation resilient asynchronous templateBEEREL PETER A·Filed 2015·Granted Jan 31, 2017·7 cites·11 claims
- 0582US9875327B2Timing violation resilient asynchronous templateBEEREL PETER A·Filed 2016·Granted Jan 23, 2018·6 cites·6 claims
- 0682US8086975B2Power aware asynchronous circuitsSHIRING KEN·Filed 2009·Granted Dec 27, 2011·27 cites·20 claims
- 0782US6785875B2Methods and apparatus for facilitating physical synthesis of an integrated circuit designFULCRUM MICROSYSTEMS INC·Filed 2003·Granted Aug 31, 2004·34 cites·99 claims
- 0879US8448105B2Clustering and fanout optimizations of asynchronous circuitsDIMOU GEORGIOS·Filed 2009·Granted May 21, 2013·14 cites·23 claims
- 0969US8972915B2Static timing analysis of template-based asynchronous circuitsPRAKASH MALLIKA·Filed 2009·Granted Mar 3, 2015·10 cites·31 claims
- 1069US7197691B2Reduced-latency soft-in/soft-out moduleUNIV SOUTHERN CALIFORNIA·Filed 2004·Granted Mar 27, 2007·16 cites·16 claims
- 1166US5931944ABranch instruction handling in a self-timed marking systemINTEL CORP·Filed 1997·Granted Aug 3, 1999·49 cites·23 claims
- 1258US5948096AApparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytesINTEL CORP·Filed 1997·Granted Sep 7, 1999·36 cites·18 claims
- 1356US2024205563A1Peripheral circuits for processing in-pixelUNIV SOUTHERN CALIFORNIA·Filed 2023·Application pending·0 cites
- 1455US8495543B2Multi-level domino, bundled data, and mixed templatesDIMOU GEORGIOS·Filed 2009·Granted Jul 23, 2013·3 cites·36 claims
- 1553US6690752B2Sequential decoder for decoding of convolutional codesUNIV SOUTHERN CALIFORNIA·Filed 2001·Granted Feb 10, 2004·9 cites·19 claims
- 1648US6526551B2Formal verification of a logic design through implicit enumeration of strongly connected componentsUNIV SOUTHERN CALIFORNIA·Filed 2001·Granted Feb 25, 2003·3 cites·35 claims
- 1745US5978899AApparatus and method for parallel processing and self-timed serial marking of variable length instructionsINTEL CORP·Filed 1997·Granted Nov 2, 1999·18 cites·37 claims
- 1840US5941982AEfficient self-timed marking of lengthy variable length instructionsINTEL CORP·Filed 1997·Granted Aug 24, 1999·13 cites·18 claims
- 1933US2002021770A1Reduced-latency soft-in/soft-out moduleFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →