Inventor · disambiguated record
Peter Mccolgan
Also filed as: MCCOLGAN PETER
12 granted patents·1 pending application·64 citations·filing 2018–2025
88Inventor score
Files withXILINX INC13
Top patents by PatentIndex Score
13 records- 0196US11336287B1Data processing engine array architecture with memory tilesXILINX INC·Filed 2021·Granted May 17, 2022·26 cites·20 claims
- 0295US11520717B1Memory tiles in data processing engine arrayXILINX INC·Filed 2021·Granted Dec 6, 2022·11 cites·20 claims
- 0394US11323391B1Multi-port stream switch for stream interconnect networkXILINX INC·Filed 2020·Granted May 3, 2022·6 cites·20 claims
- 0491US10635622B2System-on-chip interface architectureXILINX INC·Filed 2018·Granted Apr 28, 2020·10 cites·8 claims
- 0589US11848670B2Multiple partitions in a data processing arrayXILINX INC·Filed 2022·Granted Dec 19, 2023·2 cites·10 claims
- 0685US10990552B1Streaming interconnect architecture for data processing engine arrayXILINX INC·Filed 2018·Granted Apr 27, 2021·4 cites·20 claims
- 0784US11113223B1Dual mode interconnectXILINX INC·Filed 2018·Granted Sep 7, 2021·4 cites·23 claims
- 0882US2025343549A1Multiple partitions in a data processing arrayXILINX INC·Filed 2025·Application pending·0 cites
- 0976US11443091B1Data processing engines with cascade connected coresXILINX INC·Filed 2020·Granted Sep 13, 2022·1 cites·20 claims
- 1075US12401364B2Multiple partitions in a data processing arrayXILINX INC·Filed 2023·Granted Aug 26, 2025·0 cites·11 claims
- 1166US11730325B2Dual mode interconnectXILINX INC·Filed 2021·Granted Aug 22, 2023·0 cites·18 claims
- 1255US12067406B2Multiple overlays for use with a data processing arrayXILINX INC·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 1348US12164451B2Data processing array interface having interface tiles with multiple direct memory access circuitsXILINX INC·Filed 2022·Granted Dec 10, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →