Inventor · disambiguated record
Pekka Ojala
Also filed as: OJALA PEKKA · OJALA PEKKA KALERVO
6 granted patents·2 pending applications·22 citations·filing 2001–2018
78Inventor score
Top patents by PatentIndex Score
8 records- 0164US10103728B1Adaptive body biasing in CMOS circuits to extend the input common mode operating rangeEXAR CORP·Filed 2017·Granted Oct 16, 2018·1 cites·36 claims
- 0256US7057241B2Reverse-biased P/N wells isolating a CMOS inductor from the substrateEXAR CORP·Filed 2002·Granted Jun 6, 2006·9 cites·6 claims
- 0353US10418989B2Adaptive body biasing in CMOS circuits to extend the input common mode operating rangeEXAR CORP·Filed 2018·Granted Sep 17, 2019·0 cites·36 claims
- 0448US6693783B2Bounce tolerant fuse trimming circuit with controlled timingEXAR CORP·Filed 2002·Granted Feb 17, 2004·6 cites·20 claims
- 0543US8810981B2Sequential electrostatic discharge (ESD)-protection employing cascode NMOS triggered structureOJALA PEKKA KALERVO·Filed 2012·Granted Aug 19, 2014·1 cites·6 claims
- 0643US6597222B2Power down circuit for high output impedance state of I/O driverEXAR CORP·Filed 2001·Granted Jul 22, 2003·5 cites·6 claims
- 0733US2012326278A1Method to solve potential yield loss due to metal migration to wire routing nets from fiduciary marks on product during chemical-mechanical-polishing (cmp) planarization processing stepsSALDANHA OSCAR JOSEPH·Filed 2011·Application pending·0 cites
- 0831US2004085700A1Delay line and transistor with RC delay gateEXAR CORP·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →