Inventor · disambiguated record
Pervez Hassan Sagarwala
Also filed as: SAGARWALA PERVEZ H · SAGARWALA PERVEZ HASSAN
8 granted patents·177 citations·filing 1996–2001
89Inventor score
Top patents by PatentIndex Score
8 records- 0185US6759717B2CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistorST MICROELECTRONICS INC·Filed 2001·Granted Jul 6, 2004·35 cites·16 claims
- 0279US6034886AShadow memory for a SRAM and methodST MICROELECTRONICS INC·Filed 1998·Granted Mar 7, 2000·41 cites·9 claims
- 0376US6128243AShadow memory for a SRAM and methodST MICROELECTRONICS INC·Filed 1999·Granted Oct 3, 2000·34 cites·11 claims
- 0471US5929695AIntegrated circuit having selective bias of transistors for low voltage and low standby current and related methodsST MICROELECTRONICS INC·Filed 1997·Granted Jul 27, 1999·32 cites·25 claims
- 0556US5885871AMethod of making EEPROM cell structureSTMICROLELECTRONICS INC·Filed 1997·Granted Mar 23, 1999·17 cites·21 claims
- 0648US6221709B1Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistorST MICROELECTRONICS INC·Filed 1997·Granted Apr 24, 2001·10 cites·19 claims
- 0741US6518620B2EEPROM memory cell with increased dielectric integrityST MICROELECTRONICS INC·Filed 1998·Granted Feb 11, 2003·6 cites·10 claims
- 0831US5895237ANarrow isolation oxide processST MICROELECTRONICS INC·Filed 1996·Granted Apr 20, 1999·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →