Inventor · disambiguated record
Peter Schrogmeier
Also filed as: SCHROEGMEIER PETER · SCHROGMEIER PETER
29 granted patents·6 pending applications·444 citations·filing 1997–2008
96Inventor score
Top patents by PatentIndex Score
35 records- 0192US6614700B2Circuit configuration with a memory arrayINFINEON TECHNOLOGIES AG·Filed 2002·Granted Sep 2, 2003·70 cites·8 claims
- 0291US6188642B1Integrated memory having column decoder for addressing corresponding bit lineSIEMENS AG·Filed 1999·Granted Feb 13, 2001·94 cites·5 claims
- 0381US6687669B1Method of reducing voice signal interferenceFiled 1997·Granted Feb 3, 2004·99 cites·9 claims
- 0478US6804165B2Latency time switch for an S-DRAMINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 12, 2004·25 cites·19 claims
- 0574US6351419B1Integrated memory with a block writing function and global amplifiers requiring less spaceINFINEON TECHNOLOGIES AG·Filed 2000·Granted Feb 26, 2002·22 cites·4 claims
- 0671US7363561B2Method and circuit arrangement for resetting an integrated circuitINFINEON TECHNOLOGIES AG·Filed 2005·Granted Apr 22, 2008·5 cites·14 claims
- 0765US7031421B2Method and device for initializing an asynchronous latch chainINFINEON TECHNOLOGIES AG·Filed 2002·Granted Apr 18, 2006·14 cites·12 claims
- 0863US6388944B2Memory component with short access timeINFINEON TECHNOLOGIES AG·Filed 2001·Granted May 14, 2002·13 cites·13 claims
- 0962US6272035B1Integrated memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 7, 2001·13 cites·7 claims
- 1059US6359832B2Method and circuit configuration for read-write mode control of a synchronous memoryINFINEON TECHNOLOGIES AG·Filed 2001·Granted Mar 19, 2002·10 cites·6 claims
- 1156US6275445B1Synchronous integrated memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 14, 2001·9 cites·4 claims
- 1255US6401224B1Integrated circuit and method for testing itINFINEON TECHNOLOGIES AG·Filed 1999·Granted Jun 4, 2002·18 cites·10 claims
- 1352US7058840B2Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clockINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 6, 2006·5 cites·7 claims
- 1452US6480024B2Circuit configuration for programming a delay in a signal pathINFINEON TECHNOLOGIES AG·Filed 2001·Granted Nov 12, 2002·6 cites·8 claims
- 1550US7120818B2Method and device for data transferINFINEON TECHNOLOGIES AG·Filed 2002·Granted Oct 10, 2006·6 cites·16 claims
- 1649US6882554B2Integrated memory, and a method of operating an integrated memoryINFINEON TECHNOLOGIES AG·Filed 2002·Granted Apr 19, 2005·6 cites·12 claims
- 1748US6310824B1Integrated memory with two burst operation typesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Oct 30, 2001·6 cites·4 claims
- 1848US2006149989A1Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clockINFINEON TECHNOLOGIES AG·Filed 2006·Application pending·0 cites
- 1944US6285605B1Integrated memory having redundant units of memory cells, and test method for the redundant unitsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 4, 2001·4 cites·2 claims
- 2039US7751231B2Method and integrated circuit for determining the state of a resistivity changing memory cellQIMONDA AG·Filed 2008·Granted Jul 6, 2010·0 cites·15 claims
- 2139US2006181437A1Bus systemINFINEON TECHNOLOGIES AG·Filed 2005·Application pending·0 cites
- 2238US6847581B2Integrated circuit and method for operating the integrated circuitINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jan 25, 2005·1 cites·8 claims
- 2337US6437410B1Integrated memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 20, 2002·2 cites·5 claims
- 2437US6385123B1Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activatedINFINEON TECHNOLOGIES AG·Filed 2000·Granted May 7, 2002·1 cites·5 claims
- 2536US6396755B2Integrated memory with row access control to activate and precharge row lines, and method of operating such a memoryINFINEON TECHNOLOGIES AG·Filed 2001·Granted May 28, 2002·1 cites·12 claims
- 2636US6101141AIntegrated memorySIEMENS AG·Filed 1999·Granted Aug 8, 2000·5 cites·1 claims
- 2735US6144590ASemiconductor memory having differential bit linesSIEMENS AG·Filed 1999·Granted Nov 7, 2000·5 cites·9 claims
- 2835US6028815AIntegrated memorySIEMENS AG·Filed 1999·Granted Feb 22, 2000·4 cites·10 claims
- 2934US2009091968A1Integrated circuit including a memory having a data inversion circuitDIETRICH STEFAN·Filed 2007·Application pending·0 cites
- 3032US6542389B2Voltage pump with switch-on controlINFINEON TECHNOLOGIES AG·Filed 2001·Granted Apr 1, 2003·0 cites·9 claims
- 3132US6404699B1Integrated circuit having a command decoderINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jun 11, 2002·0 cites·3 claims
- 3232US6256219B1Integrated memory having memory cells disposed at crossover points of word lines and bit linesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 3, 2001·0 cites·2 claims
- 3332US2003135795A1Integrated circuit and method for operating a test configuration with an integrated circuitFiled 2003·Application pending·0 cites
- 3431US2009199043A1Error correction in an integrated circuit with an array of memory cellsSCHROGMEIER PETER·Filed 2008·Application pending·0 cites
- 3531US2001026498A1Memory configuration having a circuit for determining the activated memory arrayFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →