Inventor · disambiguated record
Philippe Boucard
Also filed as: BOUCARD PHILIPPE
29 granted patents·19 pending applications·82 citations·filing 1998–2024
95Inventor score
Top patents by PatentIndex Score
48 records- 0190US7574629B2Method and device for switching between agentsARTERIS·Filed 2005·Granted Aug 11, 2009·23 cites·11 claims
- 0288US8316171B2Network on chip (NoC) with QoS featuresBOUCARD PHILIPPE·Filed 2010·Granted Nov 20, 2012·12 cites·37 claims
- 0377US8930638B2Method and apparatus for supporting target-side security in a cache coherent systemQUALCOMM TECHNOLOGIES INC·Filed 2012·Granted Jan 6, 2015·4 cites·29 claims
- 0476US9225665B2Network on a chip socket protocolQUALCOMM TECHNOLOGIES INC·Filed 2012·Granted Dec 29, 2015·6 cites·22 claims
- 0573US9141556B2System translation look-aside buffer with request-based allocation and prefetchingQUALCOMM TECHNOLOGIES INC·Filed 2013·Granted Sep 22, 2015·2 cites·37 claims
- 0673US8441931B2Method and device for managing priority during the transmission of a messageDOUADY CESAR·Filed 2010·Granted May 14, 2013·3 cites·12 claims
- 0768US9465749B2DMA engine with STLB prefetch capabilities and tethered prefetchingQUALCOMM TECHNOLOGIES INC·Filed 2013·Granted Oct 11, 2016·1 cites·13 claims
- 0868US9396130B2System translation look-aside buffer integrated in an interconnectQUALCOMM TECHNOLOGIES INC·Filed 2013·Granted Jul 19, 2016·1 cites·23 claims
- 0965US7769027B2Method and device for managing priority during the transmission of a messageARTERIS·Filed 2004·Granted Aug 3, 2010·8 cites·13 claims
- 1063US8254380B2Managing messages transmitted in an interconnect networkBOUCARD PHILIPPE·Filed 2006·Granted Aug 28, 2012·3 cites·28 claims
- 1161US8645557B2System of interconnections for external functional blocks on a chip provided with a single configurable communication protocolDOUADY CESAR·Filed 2006·Granted Feb 4, 2014·2 cites·19 claims
- 1260US8824295B2Link between chips using virtual channels and credit based flow controlBOUCARD PHILIPPE·Filed 2011·Granted Sep 2, 2014·1 cites·9 claims
- 1357US7148728B2Digital delay device, digital oscillator clock signal generator and memory interfaceARTERIS·Filed 2004·Granted Dec 12, 2006·10 cites·16 claims
- 1455US2025363248A1Data encryption for data transfers between semiconductor dies using a keystream generatorQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1554US12513081B2Data routing for networks on a chip using virtual channels and credit restrictionsQUALCOMM INC·Filed 2024·Granted Dec 30, 2025·0 cites·18 claims
- 1654US9172656B2Method and device for managing priority during the transmission of a messageQUALCOMM TECHNOLOGIES INC·Filed 2013·Granted Oct 27, 2015·0 cites·5 claims
- 1753US12332811B1Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access managementQUALCOMM INC·Filed 2024·Granted Jun 17, 2025·0 cites·20 claims
- 1853US11940939B2Encoding byte information on a data bus with separate codeQUALCOMM INC·Filed 2022·Granted Mar 26, 2024·0 cites·22 claims
- 1952US2010180163A1Method and device for switching between agentsDOUADY CESAR·Filed 2009·Application pending·0 cites
- 2051US2010122004A1Message switching systemARTERIS·Filed 2009·Application pending·0 cites
- 2150US9608935B2Tunneling within a network-on-chip topologyQUALCOMM TECHNOLOGIES INC·Filed 2014·Granted Mar 28, 2017·0 cites·8 claims
- 2249US9882839B2Zero-latency network on chip (NoC)QUALCOMM TECHNOLOGIES INC·Filed 2015·Granted Jan 30, 2018·0 cites·30 claims
- 2349US9049124B2Zero-latency network on chip (NoC)LECLER JEAN-JACQUES·Filed 2009·Granted Jun 2, 2015·0 cites·28 claims
- 2448US2013179613A1Network on chip (noc) with qos featuresARTERIS S A·Filed 2012·Application pending·0 cites
- 2547US8031730B2System and method for transmitting a sequence of messages in an interconnection networkARTERIS·Filed 2004·Granted Oct 4, 2011·0 cites·10 claims
- 2647US7639704B2Message switching systemARTERIS·Filed 2006·Granted Dec 29, 2009·0 cites·16 claims
- 2746US9069912B2System and method of distributed initiator-local reorder buffersBOUCARD PHILIPPE·Filed 2012·Granted Jun 30, 2015·0 cites·14 claims
- 2846US2005086412A1System and method for communicating between modulesFiled 2004·Application pending·0 cites
- 2946US2005154843A1Method of managing a device for memorizing data organized in a queue, and associated deviceFiled 2004·Application pending·0 cites
- 3046US2025298756A1Method and apparatus for scalable exclusive access management in memory systemsQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3145US10606339B2Coherent interconnect power reduction using hardware controlled split snoop directoriesQUALCOMM INC·Filed 2016·Granted Mar 31, 2020·0 cites·30 claims
- 3244US9471538B2Network on a chip socket protocolQUALCOMM TECHNOLOGIES INC·Filed 2012·Granted Oct 18, 2016·0 cites·19 claims
- 3344US9177615B2Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domainBOUCARD PHILIPPE·Filed 2012·Granted Nov 3, 2015·0 cites·19 claims
- 3444US2004225490A1Device for emulating one or more integrated-circuit chipsARTERIS·Filed 2003·Application pending·0 cites
- 3544US2025284575A1Token-controlled streaming ordered write in data communicationQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3643US8788737B2Transport of PCI-ordered traffic over independent networksBOUCARD PHILIPPE·Filed 2011·Granted Jul 22, 2014·0 cites·28 claims
- 3743US2008157753A1System and method for determining the performance of an on-chip interconnection networkBOUCARD PHILIPPE·Filed 2007·Application pending·0 cites
- 3843US2021382651A1Scheduling memory transactionsQUALCOMM INC·Filed 2020·Application pending·0 cites
- 3942US2012331034A1Latency ProbeFAWAZ ALAIN·Filed 2012·Application pending·0 cites
- 4042US2005157717A1Method and system for transmitting messages in an interconnection networkFiled 2005·Application pending·0 cites
- 4142US2008028090A1System for managing messages transmitted in an on-chip interconnect networkKOK SOPHANA·Filed 2006·Application pending·0 cites
- 4241US2013002315A1Asynchronous clock adapterBOUCARD PHILIPPE·Filed 2012·Application pending·0 cites
- 4340US2007110052A1System and method for the static routing of data packet streams in an interconnect networkKOK SOPHANA·Filed 2006·Application pending·0 cites
- 4440US2007081414A1System and method of on-circuit asynchronous communication, between synchronous subcircuitsDOUADY CESAR·Filed 2006·Application pending·0 cites
- 4539US2015019776A1Selective change of pending transaction urgencyQUALCOMM TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 4634US7755920B2Electronic memory deviceARTERIS·Filed 2008·Granted Jul 13, 2010·0 cites·10 claims
- 4732US6516004B1HDLC digital data transmission protocol controllerSQWARE INC T·Filed 1998·Granted Feb 4, 2003·6 cites·2 claims
- 4830US2012290810A1Memory Access Latency MeteringLECLER JEAN-JACQUES·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →