Inventor · disambiguated record
Philip A. Bourekas
Also filed as: BOUREKAS PHILIP · BOUREKAS PHILIP A
13 granted patents·493 citations·filing 1990–2000
94Inventor score
Top patents by PatentIndex Score
13 records- 0189US6128703AMethod and apparatus for memory prefetch operation of volatile non-coherent dataINTEGRATED DEVICE TECH·Filed 1997·Granted Oct 3, 2000·166 cites·43 claims
- 0279US6598050B1Apparatus and method for limited data sharing in a multi-tasking systemINTEGRATED DEVICE TECH·Filed 2000·Granted Jul 22, 2003·28 cites·16 claims
- 0376US5317711AStructure and method for monitoring an internal cacheINTEGRATED DEVICE TECH·Filed 1991·Granted May 31, 1994·75 cites·14 claims
- 0471US5636363AHardware control structure and method for off-chip monitoring entries of an on-chip cacheINTEGRATED DEVICE TECH·Filed 1991·Granted Jun 3, 1997·57 cites·4 claims
- 0566US5694567ADirect-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bitsINTEGRATED DEVICE TECH·Filed 1995·Granted Dec 2, 1997·53 cites·20 claims
- 0653US7133951B1Alternate set of registers to service critical interrupts and operating system trapsBOUREKAS PHILIP A·Filed 2000·Granted Nov 7, 2006·6 cites·29 claims
- 0750US5175859AApparatus for disabling unused cache tag input/output pins during processor reset by sensing pull-down resistors connected to disabled pinsINTEGRATED DEVICE TECH·Filed 1990·Granted Dec 29, 1992·22 cites·5 claims
- 0849US5386579AMinimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transferINTEGRATED DEVICE TECH·Filed 1991·Granted Jan 31, 1995·25 cites·14 claims
- 0947US5553268AMemory operations priority scheme for microprocessorsINTEGRATED DEVICE TECH·Filed 1991·Granted Sep 3, 1996·22 cites·10 claims
- 1043US5649232AStructure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rateINTEGRATED DEVICE TECH·Filed 1995·Granted Jul 15, 1997·17 cites·14 claims
- 1139US5343435AUse of a data register to effectively increase the efficiency of an on-chip write bufferINTEGRATED DEVICE TECH·Filed 1991·Granted Aug 30, 1994·9 cites·2 claims
- 1235US5517659AMultiplexed status and diagnostic pins in a microprocessor with on-chip cachesINTEGRATED DEVICE TECH·Filed 1994·Granted May 14, 1996·8 cites·8 claims
- 1334US5894176AFlexible reset scheme supporting normal system operation, test and emulation modesINTEGRATED DEVICE TECH·Filed 1994·Granted Apr 13, 1999·5 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →