Inventor · disambiguated record
Philippe Flatresse
Also filed as: FLATRESSE PHILIPPE
8 granted patents·1 pending application·48 citations·filing 2003–2013
83Inventor score
Top patents by PatentIndex Score
9 records- 0188US8482070B1Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the sameFLATRESSE PHILIPPE·Filed 2012·Granted Jul 9, 2013·25 cites·10 claims
- 0280US9092590B2Method for generating a topography of an FDSOI integrated circuitCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Jul 28, 2015·8 cites·10 claims
- 0373US8570096B2Transistor substrate dynamic biasing circuitLE COZ JULIEN·Filed 2011·Granted Oct 29, 2013·6 cites·10 claims
- 0457US7622983B2Method and device for adapting the voltage of a MOS transistor bulkST MICROELECTRONICS SA·Filed 2007·Granted Nov 24, 2009·4 cites·24 claims
- 0547US6871330B2Method and device for characterizing a CMOS logic cell to be produced in a technology of the partially depleted silicon-on-insulator typeST MICROELECTRONICS SA·Filed 2003·Granted Mar 22, 2005·4 cites·27 claims
- 0642US7847623B2Device and method for power switch monitoringST MICROELECTRONICS SA·Filed 2008·Granted Dec 7, 2010·1 cites·19 claims
- 0742US7619863B2Gated thyristor and related system and methodST MICROELECTRONICS SA·Filed 2007·Granted Nov 17, 2009·0 cites·38 claims
- 0835US9911737B2Integrated circuit comprising transistors with different threshold voltagesST MICROELECTRONICS SA·Filed 2013·Granted Mar 6, 2018·0 cites·10 claims
- 0935US2006155523A1Method and device for representing a cell implemented in a partially depleted silison-on-insulator type CMOS technologyST MICROELECTRONICS SA·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →