Inventor · disambiguated record
Philip G. Neudeck
Also filed as: NEUDECK PHILIP · NEUDECK PHILIP G
21 granted patents·1 pending application·1,179 citations·filing 1994–2022
96Inventor score
Top patents by PatentIndex Score
22 records- 0196US5709745ACompound semi-conductors and controlled doping thereofOHIO AEROSPACE INST·Filed 1995·Granted Jan 20, 1998·552 cites·52 claims
- 0294US6488771B1Method for growing low-defect single crystal heteroepitaxial filmsNASA·Filed 2001·Granted Dec 3, 2002·60 cites·52 claims
- 0393US7449065B1Method for the growth of large low-defect single crystalsOHIO AEROSPACE INST·Filed 2006·Granted Nov 11, 2008·47 cites·46 claims
- 0490US5915194AMethod for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereonNASA·Filed 1997·Granted Jun 22, 1999·135 cites·24 claims
- 0589US6165874AMethod for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereonNASA·Filed 1998·Granted Dec 26, 2000·115 cites·17 claims
- 0688US6869480B1Method for the production of nanometer scale step height reference specimensNASA·Filed 2002·Granted Mar 22, 2005·50 cites·75 claims
- 0787US7935601B1Method for providing semiconductors having self-aligned ion implantNASA·Filed 2009·Granted May 3, 2011·10 cites·21 claims
- 0885US6763699B1Gas sensors using SiC semiconductors and method of fabrication thereofUS ADMINISTRATOR OF NATURAL AE·Filed 2003·Granted Jul 20, 2004·34 cites·33 claims
- 0985US6461944B2Methods for growth of relatively large step-free SiC crystal surfacesNASA·Filed 2001·Granted Oct 8, 2002·38 cites·51 claims
- 1083US10490550B1Larger-area integrated electrical metallization dielectric structures with stress-managed unit cells for more capable extreme environment semiconductor electronicsUnited States of Americas as represented by the Administrator of NASA·Filed 2017·Granted Nov 26, 2019·4 cites·14 claims
- 1183US10256202B1Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuitsNASA·Filed 2018·Granted Apr 9, 2019·8 cites·17 claims
- 1279US8841698B2Method for providing semiconductors having self-aligned ion implantNEUDECK PHILIP G·Filed 2011·Granted Sep 23, 2014·5 cites·20 claims
- 1378US6844251B2Method of forming a semiconductor device with a junction termination layerSHENAI KRISHNA·Filed 2002·Granted Jan 18, 2005·29 cites·25 claims
- 1478US5463978ACompound semiconductor and controlled doping thereofOHIO AEROSPACE INST·Filed 1994·Granted Nov 7, 1995·69 cites·59 claims
- 1574US11004802B1Reliability extreme temperature integrated circuits and method for producing the sameNASA·Filed 2018·Granted May 11, 2021·2 cites·9 claims
- 1666US9978686B1Interconnection of semiconductor devices in extreme environment microelectronic integrated circuit chipsNASA·Filed 2017·Granted May 22, 2018·1 cites·19 claims
- 1765US10122363B1Current source logic gateNASA·Filed 2017·Granted Nov 6, 2018·1 cites·20 claims
- 1859US12402369B1Mitigating detrimental mobile ion contamination effects in integrated circuitsNASA·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 1959US6783592B2Lateral movement of screw dislocations during homoepitaxial growth and devices yielded therefrom free of the detrimental effects of screw dislocationsNASA·Filed 2002·Granted Aug 31, 2004·7 cites·72 claims
- 2053US11128293B1Compensation for device property variation according to wafer locationNASA·Filed 2020·Granted Sep 21, 2021·0 cites·20 claims
- 2139US6111452AWide dynamic range RF mixers using wide bandgap semiconductorsUS ARMY·Filed 1997·Granted Aug 29, 2000·12 cites·33 claims
- 2239US2004144301A1Method for growth of bulk crystals by vapor phase epitaxyFiled 2003·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Philip G. Neudeck files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →