Inventor · disambiguated record
Philip Pan
Also filed as: PAN PHILIP · PAN PHILIP Y
56 granted patents·3 pending applications·884 citations·filing 2001–2016
99Inventor score
Top patents by PatentIndex Score
59 records- 0198US6433579B1Programmable logic integrated circuit devices with differential signaling capabilitiesALTERA CORP·Filed 2001·Granted Aug 13, 2002·136 cites·50 claims
- 0296US6825698B2Programmable high speed I/O interfaceALTERA CORP·Filed 2002·Granted Nov 30, 2004·46 cites·38 claims
- 0395US7227395B1High-performance memory interface circuit architectureALTERA CORP·Filed 2005·Granted Jun 5, 2007·22 cites·29 claims
- 0495US7167023B1Multiple data rate interface architectureALTERA CORP·Filed 2005·Granted Jan 23, 2007·20 cites·47 claims
- 0594US6911860B1On/off reference voltage switch for multiple I/O standardsALTERA CORP·Filed 2001·Granted Jun 28, 2005·59 cites·26 claims
- 0693US7116135B2Programmable high speed I/O interfaceALTERA CORP·Filed 2004·Granted Oct 3, 2006·30 cites·45 claims
- 0792US8593195B1High performance memory interface circuit architectureHUANG JOSEPH·Filed 2012·Granted Nov 26, 2013·8 cites·14 claims
- 0892US6825692B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2002·Granted Nov 30, 2004·38 cites·25 claims
- 0992US6806733B1Multiple data rate interface architectureALTERA CORP·Filed 2002·Granted Oct 19, 2004·48 cites·16 claims
- 1091US7425844B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2007·Granted Sep 16, 2008·14 cites·24 claims
- 1191US6870413B1Schmitt trigger circuit with adjustable trip point voltagesALTERA CORP·Filed 2001·Granted Mar 22, 2005·47 cites·25 claims
- 1290US7002384B1Loop circuitry with low-pass noise filterALTERA CORP·Filed 2004·Granted Feb 21, 2006·38 cites·36 claims
- 1390US6630844B1Supply voltage detection circuitALTERA CORP·Filed 2001·Granted Oct 7, 2003·33 cites·37 claims
- 1489US7315188B2Programmable high speed interfaceALTERA CORP·Filed 2006·Granted Jan 1, 2008·10 cites·39 claims
- 1589US6766505B1Parallel programming of programmable logic using register chainsALTERA CORP·Filed 2002·Granted Jul 20, 2004·39 cites·29 claims
- 1689US6661733B1Dual-port SRAM in a programmable logic deviceALTERA CORP·Filed 2001·Granted Dec 9, 2003·39 cites·33 claims
- 1787US8575957B2Multiple data rate interface architecturePAN PHILIP·Filed 2011·Granted Nov 5, 2013·5 cites·18 claims
- 1885US7215143B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2004·Granted May 8, 2007·20 cites·30 claims
- 1985US7205806B2Loop circuitry with low-pass noise filterALTERA CORP·Filed 2005·Granted Apr 17, 2007·12 cites·18 claims
- 2083US8098082B1Multiple data rate interface architecturePAN PHILIP·Filed 2010·Granted Jan 17, 2012·4 cites·20 claims
- 2182US9166589B2Multiple data rate interface architectureALTERA CORP·Filed 2013·Granted Oct 20, 2015·3 cites·17 claims
- 2282US8487665B2Programmable high-speed interfaceWANG BONNIE I·Filed 2011·Granted Jul 16, 2013·3 cites·17 claims
- 2382US7586341B2Programmable high-speed interfaceALTERA CORP·Filed 2007·Granted Sep 8, 2009·6 cites·10 claims
- 2482US6946872B1Multiple data rate interface architectureALTERA CORP·Filed 2003·Granted Sep 20, 2005·24 cites·22 claims
- 2581US7460431B1Implementation of double data rate embedded memory in programmable devicesALTERA CORP·Filed 2005·Granted Dec 2, 2008·13 cites·19 claims
- 2677US7812633B1Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic deviceALTERA CORP·Filed 2006·Granted Oct 12, 2010·8 cites·28 claims
- 2777US7391236B2Distributed memory in field-programmable gate array integrated circuit devicesALTERA CORP·Filed 2005·Granted Jun 24, 2008·9 cites·14 claims
- 2877US7200769B1Self-compensating delay chain for multiple-date-rate interfacesALTERA CORP·Filed 2002·Granted Apr 3, 2007·17 cites·35 claims
- 2976US7656191B2Distributed memory in field-programmable gate array integrated circuit devicesALTERA CORP·Filed 2008·Granted Feb 2, 2010·8 cites·13 claims
- 3076US7231536B1Control circuit for self-compensating delay chain for multiple-data-rate interfacesALTERA CORP·Filed 2004·Granted Jun 12, 2007·16 cites·16 claims
- 3176US6992947B1Dual-port SRAM in a programmable logic deviceALTERA CORP·Filed 2003·Granted Jan 31, 2006·13 cites·20 claims
- 3275US7768430B1Look-up table based memoryALTERA CORP·Filed 2008·Granted Aug 3, 2010·7 cites·24 claims
- 3374US8819607B1Method and apparatus to minimize clock tree skew in ICsALTERA CORP·Filed 2013·Granted Aug 26, 2014·5 cites·20 claims
- 3470US8064280B1Scaleable look-up table based memoryPAN PHILIP·Filed 2008·Granted Nov 22, 2011·5 cites·19 claims
- 3570US7119579B2Supply voltage detection circuitALTERA CORP·Filed 2004·Granted Oct 10, 2006·10 cites·14 claims
- 3669US6870400B1Supply voltage detection circuitALTERA CORP·Filed 2003·Granted Mar 22, 2005·11 cites·27 claims
- 3765US8644100B2Scaleable look-up table based memoryPAN PHILIP·Filed 2011·Granted Feb 4, 2014·2 cites·19 claims
- 3863US7477074B1Multiple data rate interface architectureALTERA CORP·Filed 2006·Granted Jan 13, 2009·2 cites·20 claims
- 3962US6731137B1Programmable, staged, bus hold and weak pull-up for bi-directional I/OALTERA CORP·Filed 2002·Granted May 4, 2004·9 cites·23 claims
- 4062US6714044B1Hi-speed parallel configuration of programmable logicALTERA CORP·Filed 2002·Granted Mar 30, 2004·12 cites·22 claims
- 4161US9548103B1Scaleable look-up table based memoryALTERA CORP·Filed 2015·Granted Jan 17, 2017·1 cites·20 claims
- 4260US9123437B1Scaleable look-up table based memoryALTERA CORP·Filed 2013·Granted Sep 1, 2015·1 cites·17 claims
- 4360US6747903B1Configurable decoder for addressing a memoryALTERA CORP·Filed 2002·Granted Jun 8, 2004·8 cites·27 claims
- 4459US2017005662A1Programmable High-Speed I/O InterfaceALTERA CORP·Filed 2016·Application pending·0 cites
- 4559US2017005661A1Programmable High-Speed I/O InterfaceALTERA CORP·Filed 2016·Application pending·0 cites
- 4658US9473145B2Programmable high-speed I/O interfaceALTERA CORP·Filed 2014·Granted Oct 18, 2016·0 cites·20 claims
- 4757US7859304B1Multiple data rate interface architectureALTERA CORP·Filed 2008·Granted Dec 28, 2010·1 cites·19 claims
- 4857US7725755B1Self-compensating delay chain for multiple-date-rate interfacesALTERA CORP·Filed 2007·Granted May 25, 2010·2 cites·32 claims
- 4957US6961280B1Techniques for implementing address recycling in memory circuitsALTERA CORP·Filed 2003·Granted Nov 1, 2005·9 cites·19 claims
- 5056US8829948B2Programmable high-speed I/O interfaceALTERA CORP·Filed 2013·Granted Sep 9, 2014·0 cites·20 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →