Inventor · disambiguated record
Philippe Schoenborn
Also filed as: SCHOENBORN PHILIPPE
29 granted patents·1,604 citations·filing 1990–2005
98Inventor score
Top patents by PatentIndex Score
29 records- 0198US5474648AUniform and repeatable plasma processingLSI LOGIC CORP·Filed 1994·Granted Dec 12, 1995·237 cites·30 claims
- 0297US5401350ACoil configurations for improved uniformity in inductively coupled plasma systemsLSI LOGIC CORP·Filed 1993·Granted Mar 28, 1995·370 cites·8 claims
- 0394US5902704AProcess for forming photoresist mask over integrated circuit structures with critical dimension controlLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·219 cites·13 claims
- 0494US5468296AApparatus for igniting low pressure inductively coupled plasmaLSI LOGIC CORP·Filed 1993·Granted Nov 21, 1995·80 cites·7 claims
- 0591US6350700B1Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structureLSI LOGIC CORP·Filed 2000·Granted Feb 26, 2002·59 cites·28 claims
- 0686US6503840B2Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoningLSI LOGIC CORP·Filed 2001·Granted Jan 7, 2003·40 cites·20 claims
- 0785US6673721B1Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist maskLSI LOGIC CORP·Filed 2001·Granted Jan 6, 2004·29 cites·14 claims
- 0884US5362356APlasma etching process controlLSI LOGIC CORP·Filed 1992·Granted Nov 8, 1994·85 cites·12 claims
- 0979US5639519AMethod for igniting low pressure inductively coupled plasmaLSI LOGIC CORP·Filed 1995·Granted Jun 17, 1997·40 cites·24 claims
- 1079US5298110ATrench planarization techniquesLSI LOGIC CORP·Filed 1992·Granted Mar 29, 1994·48 cites·9 claims
- 1179US5242536AAnisotropic polysilicon etching processLSI LOGIC CORP·Filed 1990·Granted Sep 7, 1993·68 cites·19 claims
- 1277US5877530AFormation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantationLSI LOGIC CORP·Filed 1996·Granted Mar 2, 1999·44 cites·10 claims
- 1375US7071113B2Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist maskLSI LOGIC CORP·Filed 2003·Granted Jul 4, 2006·16 cites·5 claims
- 1474US6713386B1Method of preventing resist poisoning in dual damascene structuresLSI LOGIC CORP·Filed 2001·Granted Mar 30, 2004·17 cites·4 claims
- 1572US6743725B1High selectivity SiC etch in integrated circuit fabricationLSI LOGIC CORP·Filed 2001·Granted Jun 1, 2004·18 cites·11 claims
- 1672US5598021AMOS structure with hot carrier reductionLSI LOGIC CORP·Filed 1995·Granted Jan 28, 1997·43 cites·9 claims
- 1772US5290396ATrench planarization techniquesLSI LOGIC CORP·Filed 1991·Granted Mar 1, 1994·37 cites·9 claims
- 1869US6576404B2Carbon-doped hard mask and method of passivating structures during semiconductor device fabricationLSI LOGIC CORP·Filed 2000·Granted Jun 10, 2003·13 cites·11 claims
- 1968US6559048B1Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoningLSI LOGIC CORP·Filed 2001·Granted May 6, 2003·15 cites·13 claims
- 2064US6846569B2Carbon-doped hard mask and method of passivating structures during semiconductor device fabricationLSI LOGIC CORP·Filed 2003·Granted Jan 25, 2005·9 cites·6 claims
- 2162US5413966AShallow trench etchLSI LOGIC CORP·Filed 1993·Granted May 9, 1995·33 cites·16 claims
- 2261US6062163APlasma initiating assemblyLSI LOGIC CORP·Filed 1997·Granted May 16, 2000·12 cites·9 claims
- 2359US5578165ACoil configurations for improved uniformity in inductively coupled plasma systemsLSI LOGIC CORP·Filed 1995·Granted Nov 26, 1996·31 cites·8 claims
- 2451US6969683B2Method of preventing resist poisoning in dual damascene structuresLSI LOGIC CORP·Filed 2003·Granted Nov 29, 2005·3 cites·16 claims
- 2550US7379836B2Method of using automated test equipment to screen for leakage inducing defects after calibration to intrinsic leakageLSI CORP·Filed 2005·Granted May 27, 2008·3 cites·13 claims
- 2649US6506670B2Self aligned gateLSI LOGIC CORP·Filed 2001·Granted Jan 14, 2003·4 cites·18 claims
- 2749US5082792AForming a physical structure on an integrated circuit device and determining its size by measurement of resistanceLSI LOGIC CORP·Filed 1990·Granted Jan 21, 1992·18 cites·10 claims
- 2844US6579777B1Method of forming local oxidation with sloped silicon recessCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jun 17, 2003·12 cites·20 claims
- 2928US5663083AProcess for making improved MOS structure with hot carrier reductionLSI LOGIC CORP·Filed 1996·Granted Sep 2, 1997·1 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →