Inventor · disambiguated record
Pin-Shyne Chin
Also filed as: CHIN PIN-SHYNE
8 granted patents·1 pending application·60 citations·filing 2001–2010
85Inventor score
Files withTAIWAN SEMICONDUCTOR MFG9
Top patents by PatentIndex Score
9 records- 0184US6528422B1Method to modify 0.25μm 1T-RAM by extra resist protect oxide (RPO) blockingTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Mar 4, 2003·32 cites·28 claims
- 0263US6815274B1Resist protect oxide structure of sub-micron salicide processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 9, 2004·8 cites·28 claims
- 0361US6790724B1Low leakage one transistor static random access memoryTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 14, 2004·9 cites·11 claims
- 0457US6852589B2Method to modify 0.25 μm 1T-RAM by extra resist protect oxide (RPO) blockingTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Feb 8, 2005·6 cites·40 claims
- 0548US7183150B2Resist protect oxide structure of sub-micron salicide processTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Feb 27, 2007·2 cites·21 claims
- 0642US7064371B2Low leakage one transistor static random access memoryTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 20, 2006·2 cites·9 claims
- 0741US6849485B1Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET deviceTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Feb 1, 2005·1 cites·26 claims
- 0837US7244641B2Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET deviceTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 17, 2007·0 cites·14 claims
- 0936US2011084391A1Reducing Device Mismatch by Adjusting Titanium FormationTAIWAN SEMICONDUCTOR MFG·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →