Inventor · disambiguated record
Pierangelo Pansana
Also filed as: PANSANA PIERANGELO
2 granted patents·22 citations·filing 1984–1987
59Inventor score
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2 records- 0152US4719184AProcess for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistorsSGS MICROELETTRONICA SPA·Filed 1987·Granted Jan 12, 1988·17 cites·2 claims
- 0225US4488931AProcess for the self-alignment of a double polycrystalline silicon layer in an integrated circuit device through an oxidation processATES COMPONENTI ELETTRON·Filed 1984·Granted Dec 18, 1984·5 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →