Inventor · disambiguated record
Pin-Nan Tseng
Also filed as: TSENG PIN-NAN
19 granted patents·1 pending application·750 citations·filing 1992–2024
96Inventor score
Top patents by PatentIndex Score
20 records- 0199US9711555B2Dual facing BSI image sensors with wafer level stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 18, 2017·31 cites·20 claims
- 0297US5575706AChemical/mechanical planarization (CMP) apparatus and polish methodTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Nov 19, 1996·255 cites·35 claims
- 0395US9728453B2Methods for hybrid wafer bonding integrated with CMOS processingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Aug 8, 2017·21 cites·19 claims
- 0492US11037978B2Dual facing BSI image sensors with wafer level stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 15, 2021·2 cites·20 claims
- 0588US5702982AMethod for making metal contacts and interconnections concurrently on semiconductor integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Dec 30, 1997·117 cites·32 claims
- 0687US2024178263A1Dual facing bsi image sensors with wafer level stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0786US10510597B2Methods for hybrid wafer bonding integrated with CMOS processingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 17, 2019·4 cites·20 claims
- 0885US5723893AMethod for fabricating double silicide gate electrode structures on CMOS-field effect transistorsTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Mar 3, 1998·87 cites·29 claims
- 0984US5756396AMethod of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnectTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted May 26, 1998·72 cites·21 claims
- 1082US10453889B2Dual facing BSI image sensors with wafer level stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Oct 22, 2019·2 cites·20 claims
- 1177US11894408B2Dual facing BSI image sensors with wafer level stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 6, 2024·0 cites·20 claims
- 1270US5547881AMethod of forming a resistor for ESD protection in a self aligned silicide processTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Aug 20, 1996·35 cites·14 claims
- 1362US6448649B1Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnectTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Sep 10, 2002·25 cites·12 claims
- 1455US5801096ASelf-aligned tungsen etch back process to minimize seams in tungsten plugsTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Sep 1, 1998·22 cites·20 claims
- 1554US5952698ALayout pattern for improved MOS device matchingTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted Sep 14, 1999·13 cites·22 claims
- 1652US5521121AOxygen plasma etch process post contact layer etch backTAIWAN SEMICONDUCTOR MFG·Filed 1995·Granted May 28, 1996·22 cites·22 claims
- 1751US5411907ACapping free metal silicide integrated processTAIWAN SEMICONDUCTOR MFG·Filed 1992·Granted May 2, 1995·17 cites·19 claims
- 1845US6169314B1Layout pattern for improved MOS device matchingTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 2, 2001·8 cites·10 claims
- 1945US5712207AProfile improvement of a metal interconnect structure on a tungsten plugTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jan 27, 1998·14 cites·18 claims
- 2032US5866481ASelective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edgeTAIWAN SEMICONDUCTOR MFG·Filed 1996·Granted Feb 2, 1999·3 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →