Inventor · disambiguated record
Po-Kuan Ho
Also filed as: HO PO-KUAN
3 granted patents·1 pending application·3 citations·filing 2017–2024
58Inventor score
Technology areasH10W
Files withTAIWAN SEMICONDUCTOR MFG CO LTD4
Top patents by PatentIndex Score
4 records- 0181US10777452B2Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Sep 15, 2020·3 cites·20 claims
- 0277US2024282625A1Interconnection structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0373US11984355B2Method for manufacturing an interconnection structure having a bottom via spacerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted May 14, 2024·0 cites·20 claims
- 0467US11488861B2Method for manufacturing an interconnect structure having a selectively formed bottom viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 1, 2022·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Po-Kuan Ho files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →