Inventor · disambiguated record
Poovaiah M. Palangappa
Also filed as: PALANGAPPA POOVAIAH · PALANGAPPA POOVAIAH M · PALANGAPPA POOVAIAH MANAVATTIRA
11 granted patents·5 pending applications·29 citations·filing 2015–2023
85Inventor score
Top patents by PatentIndex Score
16 records- 0191US12126361B2Techniques to improve latency of retry flow in memory controllersINTEL CORP·Filed 2022·Granted Oct 22, 2024·2 cites·20 claims
- 0290US11146289B2Techniques to use intrinsic information for a bit-flipping error correction control decoderINTEL CORP·Filed 2019·Granted Oct 12, 2021·10 cites·20 claims
- 0383US10547327B2Self-configuring error control codingINTEL CORP·Filed 2017·Granted Jan 28, 2020·6 cites·20 claims
- 0481US11088707B2Low density parity check (LDPC) decoder architecture with check node storage (CNS) or bounded circulantINTEL CORP·Filed 2019·Granted Aug 10, 2021·4 cites·19 claims
- 0581US10944428B2Device, system and method for determining bit reliability informationINTEL CORP·Filed 2019·Granted Mar 9, 2021·3 cites·17 claims
- 0677US11063607B2Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logicINTEL CORP·Filed 2019·Granted Jul 13, 2021·3 cites·25 claims
- 0773US11265016B2Decoding apparatus, device, method and computer programINTEL CORP·Filed 2020·Granted Mar 1, 2022·1 cites·20 claims
- 0861US2024119287A1Methods and apparatus to construct graphs from coalesced featuresINTEL CORP·Filed 2023·Application pending·0 cites
- 0954US2024134884A1Methods and apparatus for recommendation systems with anonymized datasetsINTEL CORP·Filed 2023·Application pending·0 cites
- 1051US12504912B2Soft read for NVM that is subject to destructive readsINTEL CORP·Filed 2022·Granted Dec 23, 2025·0 cites·14 claims
- 1142US10372620B2Devices, systems, and methods having high data deduplication and low read latenciesINTEL CORP·Filed 2016·Granted Aug 6, 2019·0 cites·15 claims
- 1242US2019044538A1Estimating channel asymmetry for improved low-density parity check (ldpc) performanceINTEL CORP·Filed 2018·Application pending·0 cites
- 1341US10707901B2Die-wise residual bit error rate (RBER) estimation for memoriesINTEL CORP·Filed 2019·Granted Jul 7, 2020·0 cites·17 claims
- 1439US11777530B2Methods and apparatuses for generating optimized LDPC codesINTEL CORP·Filed 2020·Granted Oct 3, 2023·0 cites·19 claims
- 1535US2022006470A1Apparatuses, Devices, Methods and Computer Programs for Generating and Employing LDPC MatricesVANAPARTHY SANTHOSH·Filed 2020·Application pending·0 cites
- 1632US2017186500A1Memory circuit defect correctionINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →