Inventor · disambiguated record
Prasanna Sundararajan
Also filed as: SUNDARARAJAN PRASANNA
38 granted patents·1,090 citations·filing 2000–2020
98Inventor score
Top patents by PatentIndex Score
38 records- 0198US6668237B1Run-time reconfigurable testing of programmable logic devicesXILINX INC·Filed 2002·Granted Dec 23, 2003·161 cites·24 claims
- 0297US7764081B1Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunityXILINX INC·Filed 2005·Granted Jul 27, 2010·51 cites·18 claims
- 0397US7328335B1Bootable programmable logic device for internal decoding of encoded configuration dataXILINX INC·Filed 2004·Granted Feb 5, 2008·94 cites·27 claims
- 0497US6920627B2Reconfiguration of a programmable logic device using internal controlXILINX INC·Filed 2003·Granted Jul 19, 2005·216 cites·15 claims
- 0596US11256515B2Techniques for accelerating compactionMARVELL ASIA PTE LTD·Filed 2020·Granted Feb 22, 2022·6 cites·20 claims
- 0696US9286221B1Heterogeneous memory systemRENIAC INC·Filed 2015·Granted Mar 15, 2016·25 cites·25 claims
- 0796US8473880B1Synchronization of parallel memory accesses in a dataflow circuitBENNETT DAVID W·Filed 2010·Granted Jun 25, 2013·58 cites·19 claims
- 0896US7852107B1Single event upset mitigationXILINX INC·Filed 2010·Granted Dec 14, 2010·21 cites·20 claims
- 0995US7971072B1Secure exchange of IP coresXILINX INC·Filed 2005·Granted Jun 28, 2011·43 cites·20 claims
- 1093US10049035B1Stream memory management unit (SMMU)RENIAC INC·Filed 2016·Granted Aug 14, 2018·13 cites·27 claims
- 1193US7788502B1Method and system for secure exchange of IP coresXILINX INC·Filed 2005·Granted Aug 31, 2010·35 cites·20 claims
- 1293US7689726B1Bootable integrated circuit device for readback encoding of configuration dataXILINX INC·Filed 2004·Granted Mar 30, 2010·53 cites·22 claims
- 1390US8468510B1Optimization of cache architecture generated from a high-level language descriptionSUNDARARAJAN PRASANNA·Filed 2009·Granted Jun 18, 2013·27 cites·16 claims
- 1489US9262325B1Heterogeneous memory systemRENIAC INC·Filed 2015·Granted Feb 16, 2016·7 cites·20 claims
- 1588US9378003B1Compiler directed cache coherence for many caches generated from high-level language source codeSUNDARARAJAN PRASANNA·Filed 2009·Granted Jun 28, 2016·21 cites·20 claims
- 1688US7227378B2Reconfiguration of a programmable logic device using internal controlXILINX INC·Filed 2005·Granted Jun 5, 2007·15 cites·15 claims
- 1783US6530071B1Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable coresXILINX INC·Filed 2000·Granted Mar 4, 2003·37 cites·16 claims
- 1882US7406673B1Method and system for identifying essential configuration bitsXILINX INC·Filed 2004·Granted Jul 29, 2008·31 cites·46 claims
- 1981US7813912B1Profiling a hardware system generated by compiling a high level language onto a programmable logic deviceXILINX INC·Filed 2007·Granted Oct 12, 2010·11 cites·20 claims
- 2081US7343578B1Method and system for generating a bitstream view of a designXILINX INC·Filed 2004·Granted Mar 11, 2008·30 cites·39 claims
- 2181US7249010B1Methods of estimating susceptibility to single event upsets for a design implemented in an FPGAXILINX INC·Filed 2003·Granted Jul 24, 2007·31 cites·21 claims
- 2280US7930662B1Methods for automatically generating fault mitigation strategies for electronic system designsXILINX INC·Filed 2008·Granted Apr 19, 2011·10 cites·18 claims
- 2378US7539914B1Method of refreshing configuration data in an integrated circuitXILINX INC·Filed 2006·Granted May 26, 2009·11 cites·18 claims
- 2478US7386826B1Using redundant routing to reduce susceptibility to single event upsets in PLD designsXILINX INC·Filed 2003·Granted Jun 10, 2008·17 cites·27 claims
- 2578US7367007B1Method of routing a design to increase the quality of the designXILINX INC·Filed 2005·Granted Apr 29, 2008·9 cites·11 claims
- 2677US7111215B1Methods of reducing the susceptibility of PLD designs to single event upsetsXILINX INC·Filed 2004·Granted Sep 19, 2006·15 cites·64 claims
- 2774US8104011B1Method of routing a design to increase the quality of the designSUNDARARAJAN PRASANNA·Filed 2008·Granted Jan 24, 2012·7 cites·19 claims
- 2870US11429595B2Persistence of write requests in a database proxyMARVELL ASIA PTE LTD·Filed 2020·Granted Aug 30, 2022·1 cites·14 claims
- 2970US11126600B2System and method to accelerate compactionRENIAC INC·Filed 2018·Granted Sep 21, 2021·1 cites·22 claims
- 3069US10931587B2Systems and methods for congestion control in a networkRENIAC INC·Filed 2018·Granted Feb 23, 2021·1 cites·20 claims
- 3169US7519823B1Concealed, non-intrusive watermarks for configuration bitstreamsXILINX INC·Filed 2004·Granted Apr 14, 2009·14 cites·19 claims
- 3268US9043557B1Heterogeneous memory systemRENIAC INC·Filed 2013·Granted May 26, 2015·2 cites·20 claims
- 3364US8443344B1Methods for identifying gating opportunities from a high-level language program and generating a hardware definitionSUNDARARAJAN PRASANNA·Filed 2008·Granted May 14, 2013·3 cites·14 claims
- 3464US6665766B1Adaptable configuration interface for a programmable logic deviceXILINX INC·Filed 2000·Granted Dec 16, 2003·10 cites·12 claims
- 3563US8473904B1Generation of cache architecture from a high-level language descriptionSUNDARARAJAN PRASANNA·Filed 2008·Granted Jun 25, 2013·3 cites·19 claims
- 3650US11044314B2System and method for a database proxyRENIAC INC·Filed 2019·Granted Jun 22, 2021·0 cites·20 claims
- 3743US10237350B2System and method for a database proxyRENIAC INC·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 3839US11349922B2System and method for a database proxyMARVELL ASIA PTE LTD·Filed 2019·Granted May 31, 2022·0 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →