Inventor · disambiguated record
Puneet Kohli
Also filed as: KOHLI PUNEET
14 granted patents·7 pending applications·189 citations·filing 2003–2022
91Inventor score
Top patents by PatentIndex Score
21 records- 0197US7960238B2Multiple indium implant methods and devices and integrated circuits therefromTEXAS INSTRUMENTS INC·Filed 2008·Granted Jun 14, 2011·118 cites·19 claims
- 0291US7737015B2Formation of fully silicided gate with oxide barrier on the source/drain silicide regionsTEXAS INSTRUMENTS INC·Filed 2007·Granted Jun 15, 2010·25 cites·33 claims
- 0389US12159372B2Systems and methods of multiview style transferLEIA INC·Filed 2022·Granted Dec 3, 2024·3 cites·28 claims
- 0483US7736983B2High threshold NMOS source-drain formation with As, P and C to reduce damageTEXAS INSTRUMENTS INC·Filed 2008·Granted Jun 15, 2010·9 cites·20 claims
- 0583US7560379B2Semiconductive device fabricated using a raised layer to silicide the gateTEXAS INSTRUMENTS INC·Filed 2006·Granted Jul 14, 2009·12 cites·18 claims
- 0680US7846783B2Use of poly resistor implant to dope poly gatesTEXAS INSTRUMENTS INC·Filed 2008·Granted Dec 7, 2010·8 cites·12 claims
- 0779US7163878B2Ultra-shallow arsenic junction formation in silicon germaniumTEXAS INSTRUMENTS INC·Filed 2005·Granted Jan 16, 2007·6 cites·18 claims
- 0871US7531436B2Highly conductive shallow junction formationTEXAS INSTRUMENTS INC·Filed 2005·Granted May 12, 2009·3 cites·16 claims
- 0965US7524777B2Method for manufacturing an isolation structure using an energy beam treatmentTEXAS INSTRUMENTS INC·Filed 2006·Granted Apr 28, 2009·3 cites·20 claims
- 1062US7611939B2Semiconductor device manufactured using a laminated stress layerTEXAS INSTRUMENTS INC·Filed 2007·Granted Nov 3, 2009·2 cites·15 claims
- 1158US2004268349A1Systems, methods and computer program products for assigning at least one task to at least one shiftSABRE INC·Filed 2003·Application pending·0 cites
- 1257US2004193472A1Systems, methods and computer program products for generating at least one shift scheduleSABRE INC·Filed 2003·Application pending·0 cites
- 1354US2009224319A1Highly Conductive Shallow Junction FormationTEXAS INSTRUMENTS INC·Filed 2009·Application pending·0 cites
- 1444US7897496B2Semiconductor doping with reduced gate edge diode leakageTEXAS INSTRUMENTS INC·Filed 2007·Granted Mar 1, 2011·0 cites·17 claims
- 1542US2010084712A1Multiple spacer and carbon implant comprising process and semiconductor devices therefromTEXAS INSTRUMENTS INC·Filed 2008·Application pending·0 cites
- 1642US2008076227A1Method for forming a pre-metal dielectric layer using an energy beam treatmentTEXAS INSTRUMENTS INC·Filed 2006·Application pending·0 cites
- 1740US9059032B2SRAM cell parameter optimizationHOUSTON THEODORE W·Filed 2011·Granted Jun 16, 2015·0 cites·14 claims
- 1840US7465635B2Method for manufacturing a gate sidewall spacer using an energy beam treatmentTEXAS INSTRUMENTS INC·Filed 2006·Granted Dec 16, 2008·0 cites·17 claims
- 1935US2009101988A1Bipolar transistors with resistorsTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 2034US2008268628A1N-type semiconductor component with improved dopant implantation profile and method of forming sameKOHLI PUNEET·Filed 2007·Application pending·0 cites
- 2132US8217426B2Bipolar transistors with resistorsKOHLI PUNEET·Filed 2010·Granted Jul 10, 2012·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →