Inventor · disambiguated record
Puthiya K. Nizar
Also filed as: NIZAR PUTHIYA K · NIZAR PUTHIYA KOTTAL
19 granted patents·1,888 citations·filing 1994–2001
97Inventor score
Top patents by PatentIndex Score
19 records- 0196US5615404ASystem having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripheralsINTEL CORP·Filed 1994·Granted Mar 25, 1997·493 cites·6 claims
- 0294US6636957B2Method and apparatus for configuring and initializing a memory device and a memory channelINTEL CORP·Filed 2001·Granted Oct 21, 2003·88 cites·10 claims
- 0390US6889284B1Method and apparatus for supporting SDRAM memoryINTEL CORP·Filed 1999·Granted May 3, 2005·193 cites·22 claims
- 0488US6467013B1Memory transceiver to couple an additional memory channel to an existing memory channelINTEL CORP·Filed 1999·Granted Oct 15, 2002·142 cites·18 claims
- 0588US6212611B1Method and apparatus for providing a pipelined memory controllerINTEL CORP·Filed 1998·Granted Apr 3, 2001·134 cites·23 claims
- 0687US6442698B2Method and apparatus for power management in a memory subsystemINTEL CORP·Filed 1998·Granted Aug 27, 2002·115 cites·32 claims
- 0787US6226729B1Method and apparatus for configuring and initializing a memory device and a memory channelINTEL CORP·Filed 1998·Granted May 1, 2001·116 cites·26 claims
- 0886US5742847AM&A for dynamically generating and maintaining frame based polling schedules for polling isochronous and asynchronous functions that guaranty latencies and bandwidths to the isochronous functionsINTEL CORP·Filed 1994·Granted Apr 21, 1998·124 cites·20 claims
- 0981US6252821B1Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devicesINTEL CORP·Filed 1999·Granted Jun 26, 2001·48 cites·24 claims
- 1081US5809340AAdaptively generating timing signals for access to various memory devices based on stored profilesPACKARD BELL NEC·Filed 1997·Granted Sep 15, 1998·99 cites·5 claims
- 1176US5694555AMethod and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packetsINTEL CORP·Filed 1996·Granted Dec 2, 1997·92 cites·18 claims
- 1275US6470238B1Method and apparatus to control device temperatureINTEL CORP·Filed 1999·Granted Oct 22, 2002·79 cites·56 claims
- 1372US6532526B2Method and apparatus for configuring a memory device and a memory channel using configuration space registersINTEL CORP·Filed 2001·Granted Mar 11, 2003·17 cites·8 claims
- 1471US6378056B2Method and apparatus for configuring a memory device and a memory channel using configuration space registersINTEL CORP·Filed 1998·Granted Apr 23, 2002·27 cites·16 claims
- 1567US6230274B1Method and apparatus for restoring a memory device channel when exiting a low power stateINTEL CORP·Filed 1998·Granted May 8, 2001·50 cites·33 claims
- 1665US5909556AM&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packetsINTEL CORP·Filed 1997·Granted Jun 1, 1999·44 cites·12 claims
- 1742US6047355ASymmetric multiprocessing system with unified environment and distributed system functionsINTEL CORP·Filed 1997·Granted Apr 4, 2000·8 cites·13 claims
- 1841US6516396B1Means to extend tTR range of RDRAMS via the RDRAM memory controllerINTEL CORP·Filed 1999·Granted Feb 4, 2003·12 cites·36 claims
- 1939US5522069ASymmetric multiprocessing system with unified environment and distributed system functionsZENITH DATA SYSTEMS CORP·Filed 1994·Granted May 28, 1996·7 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →