Inventor · disambiguated record
Rajat Agarwal
Also filed as: AGARWAL RAJAT
79 granted patents·20 pending applications·536 citations·filing 2004–2025
99Inventor score
Files withINTEL CORP75AGARWAL RAJAT3HOLLMAN FAMILY ADVISORS LLC3RAMANUJAN RAJ K2TEXAS INSTRUMENTS INC2
Top patents by PatentIndex Score
99 records- 0198US11314589B2Read retry to selectively disable on-die ECCINTEL CORP·Filed 2020·Granted Apr 26, 2022·8 cites·21 claims
- 0298US9043674B2Error detection and correction apparatus and methodINTEL CORP·Filed 2012·Granted May 26, 2015·71 cites·24 claims
- 0397US10872011B2Internal error checking and correction (ECC) with extra system bitsINTEL CORP·Filed 2017·Granted Dec 22, 2020·27 cites·23 claims
- 0496US7644347B2Silent data corruption mitigation using error correction code with embedded signaling fault detectionINTEL CORP·Filed 2005·Granted Jan 5, 2010·84 cites·19 claims
- 0595US9691505B2Dynamic application of error correction code (ECC) based on error typeINTEL CORP·Filed 2015·Granted Jun 27, 2017·21 cites·20 claims
- 0695US9378142B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesRAMANUJAN RAJ K·Filed 2011·Granted Jun 28, 2016·27 cites·32 claims
- 0794US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 0894US9257364B2Integrated heat spreader that maximizes heat transfer from a multi-chip packageAHUJA SANDEEP·Filed 2012·Granted Feb 9, 2016·34 cites·19 claims
- 0993US11966286B2Read retry to selectively disable on-die ECCINTEL CORP·Filed 2022·Granted Apr 23, 2024·2 cites·20 claims
- 1093US11557541B2Interconnect architecture with silicon interposer and EMIBINTEL CORP·Filed 2018·Granted Jan 17, 2023·6 cites·25 claims
- 1193US9646910B2Integrated heat spreader that maximizes heat transfer from a multi-chip packageINTEL CORP·Filed 2016·Granted May 9, 2017·13 cites·21 claims
- 1292US11397692B2Low overhead integrity protection with high availability for trust domainsINTEL CORP·Filed 2018·Granted Jul 26, 2022·8 cites·21 claims
- 1392US7734980B2Mitigating silent data corruption in a buffered memory module architectureINTEL CORP·Filed 2005·Granted Jun 8, 2010·30 cites·27 claims
- 1491US12235720B2Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)INTEL CORP·Filed 2020·Granted Feb 25, 2025·3 cites·20 claims
- 1591US11010304B2Memory with reduced exposure to manufacturing related data corruption errorsINTEL CORP·Filed 2018·Granted May 18, 2021·9 cites·17 claims
- 1691US10275001B2Thermal throttling of electronic devicesINTEL CORP·Filed 2015·Granted Apr 30, 2019·15 cites·16 claims
- 1787US10102126B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesINTEL CORP·Filed 2016·Granted Oct 16, 2018·4 cites·20 claims
- 1887US8122265B2Power management using adaptive thermal throttlingRADHAKRISHNAN SIVAKUMAR·Filed 2006·Granted Feb 21, 2012·20 cites·22 claims
- 1986US10593019B2Method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded imagesSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Mar 17, 2020·7 cites·24 claims
- 2086US7587625B2Memory replay mechanismINTEL CORP·Filed 2006·Granted Sep 8, 2009·19 cites·30 claims
- 2185US10402336B2System, apparatus and method for overriding of non-locality-based instruction handlingINTEL CORP·Filed 2017·Granted Sep 3, 2019·4 cites·20 claims
- 2284US10579464B2Method and apparatus for partial cache line sparingINTEL CORP·Filed 2018·Granted Mar 3, 2020·3 cites·26 claims
- 2384US10198354B2Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memoryINTEL CORP·Filed 2017·Granted Feb 5, 2019·4 cites·25 claims
- 2482US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 2581US12386748B2Selective fill for logical control over hardware multilevel memoryINTEL CORP·Filed 2022·Granted Aug 12, 2025·1 cites·20 claims
- 2681US12347783B2Interconnect architecture with silicon interposer and EMIBINTEL CORP·Filed 2024·Granted Jul 1, 2025·0 cites·20 claims
- 2780US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
- 2880US7444479B2Fully buffered DIMM read data substitution for write acknowledgementALEXANDER JAMES W·Filed 2005·Granted Oct 28, 2008·10 cites·19 claims
- 2979US8041898B2Method, system and apparatus for reducing memory traffic in a distributed memory systemINTEL CORP·Filed 2008·Granted Oct 18, 2011·10 cites·15 claims
- 3078US11901299B2Interconnect architecture with silicon interposer and EMIBINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·25 claims
- 3178US9910728B2Method and apparatus for partial cache line sparingINTEL CORP·Filed 2015·Granted Mar 6, 2018·2 cites·25 claims
- 3278US9195551B2Enhanced storage of metadata utilizing improved error detection and correction in computer memoryDAS DEBALEENA·Filed 2012·Granted Nov 24, 2015·7 cites·22 claims
- 3378US7644248B2Mechanism to generate logically dedicated read and write channels in a memory controllerINTEL CORP·Filed 2006·Granted Jan 5, 2010·14 cites·18 claims
- 3478US2025337391A1Nonlinearity cancellation circuit for active filtersTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 3577US10884958B2DIMM for a high bandwidth memory channelINTEL CORP·Filed 2018·Granted Jan 5, 2021·2 cites·18 claims
- 3677US10725861B2Error correction code memory securityINTEL CORP·Filed 2018·Granted Jul 28, 2020·3 cites·24 claims
- 3775US8438452B2Poison bit error checking code schemeAGARWAL RAJAT·Filed 2008·Granted May 7, 2013·8 cites·20 claims
- 3875US2025094275A1Efficient security metadata encoding in error correcting code (ecc) memory without dedicated ecc bitsINTEL CORP·Filed 2024·Application pending·0 cites
- 3974US12360847B2Adaptive internal error scrubbing and error handlingINTEL CORP·Filed 2020·Granted Jul 15, 2025·1 cites·19 claims
- 4074US10901899B2Reducing conflicts in direct mapped cachesINTEL CORP·Filed 2019·Granted Jan 26, 2021·1 cites·20 claims
- 4174US7516349B2Synchronized memory channels with unidirectional linksINTEL CORP·Filed 2005·Granted Apr 7, 2009·6 cites·17 claims
- 4273US12066888B2Efficient security metadata encoding in error correcting code (ECC) memory without dedicated ECC bitsINTEL CORP·Filed 2022·Granted Aug 20, 2024·0 cites·26 claims
- 4372US12238221B2Cryptographic system memory managementINTEL CORP·Filed 2021·Granted Feb 25, 2025·0 cites·20 claims
- 4471US12355411B2Nonlinearity cancellation circuit for active filtersTEXAS INSTRUMENTS INC·Filed 2023·Granted Jul 8, 2025·0 cites·18 claims
- 4571US10296457B2Reducing conflicts in direct mapped cachesINTEL CORP·Filed 2017·Granted May 21, 2019·1 cites·18 claims
- 4670US11088846B2Key rotating trees with split counters for efficient hardware replay protectionINTEL CORP·Filed 2019·Granted Aug 10, 2021·1 cites·21 claims
- 4770US10409727B2System, apparatus and method for selective enabling of locality-based instruction handlingINTEL CORP·Filed 2017·Granted Sep 10, 2019·1 cites·19 claims
- 4869US8060692B2Memory controller using time-staggered lockstep sub-channels with buffered memoryCHRISTENSON BRUCE A·Filed 2008·Granted Nov 15, 2011·7 cites·25 claims
- 4968US12254203B2Message authentication Galois integrity and correction (MAGIC) for lightweight row hammer mitigationINTEL CORP·Filed 2022·Granted Mar 18, 2025·0 cites·20 claims
- 5068US9613722B2Method and apparatus for reverse memory sparingINTEL CORP·Filed 2014·Granted Apr 4, 2017·2 cites·24 claims
Showing the top 50 of 99 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →