Inventor · disambiguated record
Rajesh Subraya Aiyandra
Also filed as: AIYANDRA RAJESH · AIYANDRA RAJESH SUBRAYA
10 granted patents·2 pending applications·29 citations·filing 2016–2022
85Inventor score
Files withDIALOG SEMICONDUCTOR UK LTD12
Top patents by PatentIndex Score
12 records- 0188US10083926B1Stress relief solutions on WLCSP large/bulk copper plane designDIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Sep 25, 2018·11 cites·12 claims
- 0286US10797012B2Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devicesDIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Oct 6, 2020·5 cites·3 claims
- 0385US10636742B2Very thin embedded trace substrate-system in package (SIP)DIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Apr 28, 2020·4 cites·16 claims
- 0482US10764989B1Thermal enhancement of exposed die-down packageDIALOG SEMICONDUCTOR UK LTD·Filed 2019·Granted Sep 1, 2020·5 cites·18 claims
- 0579US11495567B2Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devicesDIALOG SEMICONDUCTOR UK LTD·Filed 2020·Granted Nov 8, 2022·1 cites·6 claims
- 0671US12100679B2Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devicesDIALOG SEMICONDUCTOR UK LTD·Filed 2022·Granted Sep 24, 2024·0 cites·20 claims
- 0767US10396004B2Reduction of cross talk in WLCSP's through laser drilled techniqueDIALOG SEMICONDUCTOR UK LTD·Filed 2018·Granted Aug 27, 2019·1 cites·29 claims
- 0865US10410996B2Integrated circuit package for assembling various dice in a single IC packageDIALOG SEMICONDUCTOR UK LTD·Filed 2016·Granted Sep 10, 2019·2 cites·20 claims
- 0960US10607912B2Reduction of cross talk in WLCSP's through laser drilled techniqueDIALOG SEMICONDUCTOR UK LTD·Filed 2019·Granted Mar 31, 2020·0 cites·23 claims
- 1058US11309255B2Very thin embedded trace substrate-system in package (SIP)DIALOG SEMICONDUCTOR UK LTD·Filed 2020·Granted Apr 19, 2022·0 cites·14 claims
- 1134US2019259689A1Re-Routable Clip for Leadframe Based ProductDIALOG SEMICONDUCTOR UK LTD·Filed 2018·Application pending·0 cites
- 1232US2018025965A1WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method ThereforDIALOG SEMICONDUCTOR UK LTD·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →