Inventor · disambiguated record
Randall Bach
Also filed as: BACH RANDALL · BACH RANDALL E
11 granted patents·314 citations·filing 1985–2005
92Inventor score
Top patents by PatentIndex Score
11 records- 0187US4701920ABuilt-in self-test system for VLSI circuit chipsETA SYSTEMS INC·Filed 1985·Granted Oct 20, 1987·97 cites·30 claims
- 0286US7106073B1Method and system for area efficient charge-based capacitance measurementLSI LOGIC CORP·Filed 2005·Granted Sep 12, 2006·15 cites·24 claims
- 0380US4760292ATemperature compensated output bufferETA SYSTEMS INC·Filed 1986·Granted Jul 26, 1988·28 cites·12 claims
- 0477US5843813AI/O driver design for simultaneous switching noise minimization and ESD performance enhancementLSI LOGIC CORP·Filed 1996·Granted Dec 1, 1998·38 cites·5 claims
- 0574US6544807B1Process monitor with statistically selected ring oscillatorLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·17 cites·5 claims
- 0674US5592104AOutput buffer having transmission gate and isolated supply terminalsLSI LOGIC CORP·Filed 1995·Granted Jan 7, 1997·30 cites·6 claims
- 0766US6493851B1Method and apparatus for indentifying causes of poor silicon-to-simulation correlationLSI LOGIC CORP·Filed 2001·Granted Dec 10, 2002·12 cites·23 claims
- 0860US6114903ALayout architecture for core I/O bufferLSI LOGIC CORP·Filed 1998·Granted Sep 5, 2000·26 cites·25 claims
- 0948US5654895AProcess monitor usig impedance controlled I/O controllerLSI LOGIC CORP·Filed 1996·Granted Aug 5, 1997·14 cites·15 claims
- 1047US5751161AUpdate scheme for impedance controlled I/O buffersLSI LOGIC CORP·Filed 1996·Granted May 12, 1998·22 cites·13 claims
- 1146US4769558AIntegrated circuit clock bus layout delay systemETA SYSTEMS INC·Filed 1986·Granted Sep 6, 1988·15 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →