Inventor · disambiguated record
Rasoju Veerabadra Chary
Also filed as: CHARY RASOJU V · CHARY RASOJU VEERABADRA
8 granted patents·4 pending applications·63 citations·filing 2011–2014
86Inventor score
Top patents by PatentIndex Score
12 records- 0191US9177633B2Bit line write assist for static random access memory architecturesLSI CORP·Filed 2014·Granted Nov 3, 2015·16 cites·19 claims
- 0288US8923090B1Address decoding circuits for reducing address and memory enable setup timeLSI CORP·Filed 2013·Granted Dec 30, 2014·12 cites·21 claims
- 0384US8724421B2Dual rail power supply scheme for memoriesEVANS DONALD A·Filed 2012·Granted May 13, 2014·11 cites·21 claims
- 0482US9111637B1Differential latch word line assist for SRAMLSI CORP·Filed 2014·Granted Aug 18, 2015·8 cites·20 claims
- 0574US8773927B2Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delayEVANS DONALD ALBERT·Filed 2012·Granted Jul 8, 2014·7 cites·16 claims
- 0671US9177635B1Dual rail single-ended read data paths for static random access memoriesLSI CORP·Filed 2014·Granted Nov 3, 2015·4 cites·11 claims
- 0762US8462562B1Memory device with area efficient power gating circuitryGOEL ANKUR·Filed 2011·Granted Jun 11, 2013·3 cites·20 claims
- 0857US8787099B2Adjusting access times to memory cells based on characterized word-line delay and gate delayEVANS DONALD ALBERT·Filed 2012·Granted Jul 22, 2014·2 cites·14 claims
- 0937US2015138864A1Memory architecture with alternating segments and multiple bitlinesLSI CORP·Filed 2013·Application pending·0 cites
- 1037US2015302918A1Word line decoders for dual rail static random access memoriesLSI CORP·Filed 2014·Application pending·0 cites
- 1137US2015138863A1Interleaved write assist for hierarchical bitline sram architecturesLSI CORP·Filed 2013·Application pending·0 cites
- 1236US2015138876A1Global bitline write assist for sram architecturesLSI CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →