Inventor · disambiguated record
Ratan K. Choudhury
Also filed as: CHOUDHURY RATAN · CHOUDHURY RATAN K
7 granted patents·2 pending applications·758 citations·filing 1993–2003
89Inventor score
Files withLSI LOGIC CORP7
Top patents by PatentIndex Score
9 records- 0197US5681779AMethod of doping metal layers for electromigration resistanceLSI LOGIC CORP·Filed 1994·Granted Oct 28, 1997·542 cites·23 claims
- 0280US5497076ADetermination of failure criteria based upon grain boundary electromigration in metal alloy filmsLSI LOGIC CORP·Filed 1993·Granted Mar 5, 1996·59 cites·10 claims
- 0378US6109775AMethod for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereonLSI LOGIC CORP·Filed 1997·Granted Aug 29, 2000·60 cites·18 claims
- 0471US5525837AReliable metallization with barrier for semiconductorsLSI LOGIC CORP·Filed 1995·Granted Jun 11, 1996·39 cites·12 claims
- 0569US5614437AMethod for fabricating reliable metallization with Ta-Si-N barrier for semiconductorsLSI LOGIC CORP·Filed 1995·Granted Mar 25, 1997·36 cites·19 claims
- 0652US5789783AMultilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protectionLSI LOGIC CORP·Filed 1996·Granted Aug 4, 1998·19 cites·20 claims
- 0736US2004111244A1Algorithm for fast determination of suspicious cites inside interconnect segments with the high probability of nucleation electromigration-induced voidsFiled 2002·Application pending·0 cites
- 0832US6303995B1Sidewall structure for metal interconnect and method of making sameLSI LOGIC CORP·Filed 1996·Granted Oct 16, 2001·3 cites·3 claims
- 0931US2005006770A1Copper-low-K dual damascene interconnect with improved reliabilityFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →