Inventor · disambiguated record
Ravindranath Doddi
Also filed as: DODDI RAVINDRANATH
15 granted patents·3 pending applications·3 citations·filing 2022–2024
84Inventor score
Files withQUALCOMM INC18
Top patents by PatentIndex Score
18 records- 0189US12164448B2Mechanism to reduce exit latency for deeper power saving modes L2 in PCIeQUALCOMM INC·Filed 2022·Granted Dec 10, 2024·2 cites·28 claims
- 0282US12079061B2Power management for peripheral component interconnectQUALCOMM INC·Filed 2022·Granted Sep 3, 2024·1 cites·20 claims
- 0365US12430199B2Flow control between peripheral component interconnect express devicesQUALCOMM INC·Filed 2022·Granted Sep 30, 2025·0 cites·22 claims
- 0463US12399853B2Mechanism to improve link initialization timeQUALCOMM INC·Filed 2023·Granted Aug 26, 2025·0 cites·14 claims
- 0560US12430280B2Mechanism to improve the reliability of sideband in chipletsQUALCOMM INC·Filed 2023·Granted Sep 30, 2025·0 cites·27 claims
- 0660US12153527B2Data rate increase for faulty lane recovery in multiple lane data linksQUALCOMM INC·Filed 2022·Granted Nov 26, 2024·0 cites·24 claims
- 0759US12314204B2Single clock lane operation for a main band of a die-to-die connectionQUALCOMM INC·Filed 2023·Granted May 27, 2025·0 cites·24 claims
- 0858US12373359B2Mechanism to enhance PCIe generation switchingQUALCOMM INC·Filed 2023·Granted Jul 29, 2025·0 cites·30 claims
- 0957US12019577B2Latency reduction for link speed switching in multiple lane data linksQUALCOMM INC·Filed 2022·Granted Jun 25, 2024·0 cites·20 claims
- 1056US12386382B2Reduced training for main band chip module interconnection clock linesQUALCOMM INC·Filed 2023·Granted Aug 12, 2025·0 cites·23 claims
- 1153US12499077B2Variable link width in two directions for main band chip module connectionQUALCOMM INC·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 1253US11934335B2Power management for peripheral component interconnectQUALCOMM INC·Filed 2022·Granted Mar 19, 2024·0 cites·20 claims
- 1353US2025363282A1Alternative mainband modeQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1452US12417196B2Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) systemQUALCOMM INC·Filed 2023·Granted Sep 16, 2025·0 cites·23 claims
- 1551US12423252B2Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) systemQUALCOMM INC·Filed 2023·Granted Sep 23, 2025·0 cites·12 claims
- 1650US2024264965A1Channel direction management for bus interfacesQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1749US12380047B2Expanded data link width for main band chip module connection in alternate modesQUALCOMM INC·Filed 2023·Granted Aug 5, 2025·0 cites·25 claims
- 1846US2024354141A1Virtual data linksQUALCOMM INC·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →