Inventor · disambiguated record
Raghu G. Gopalakrishnasetty
Also filed as: GOPALAKRISHNASETTY RAGHU G · GOPALAKRISHNASETTY RAGHU GAURAV
21 granted patents·23 citations·filing 2013–2019
91Inventor score
Files withIBM21
Top patents by PatentIndex Score
21 records- 0190US10060971B2Adjusting latency in a scan cellIBM·Filed 2016·Granted Aug 28, 2018·4 cites·20 claims
- 0282US10746794B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted Aug 18, 2020·2 cites·8 claims
- 0382US10649028B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted May 12, 2020·2 cites·6 claims
- 0482US10088524B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2016·Granted Oct 2, 2018·2 cites·12 claims
- 0581US9322876B2Control test point for timing stability during scan captureIBM·Filed 2015·Granted Apr 26, 2016·3 cites·4 claims
- 0680US9194915B2Control test point for timing stability during scan captureIBM·Filed 2013·Granted Nov 24, 2015·5 cites·13 claims
- 0775US10216885B2Adjusting scan connections based on scan control locationsIBM·Filed 2017·Granted Feb 26, 2019·1 cites·17 claims
- 0866US10303631B2Self-moderating bus arbitration architectureIBM·Filed 2016·Granted May 28, 2019·1 cites·21 claims
- 0962US10739401B2Logic built in self test circuitry for use in an integrated circuit with scan chainsIBM·Filed 2018·Granted Aug 11, 2020·0 cites·12 claims
- 1061US11112854B2Operating pulsed latches on a variable power supplyIBM·Filed 2019·Granted Sep 7, 2021·0 cites·19 claims
- 1160US9218447B2Automatic test pattern generation (ATPG) considering crosstalk effectsIBM·Filed 2014·Granted Dec 22, 2015·2 cites·20 claims
- 1259US10527674B2Circuit structures to resolve random testabilityIBM·Filed 2017·Granted Jan 7, 2020·0 cites·10 claims
- 1358US10816599B2Dynamically power noise adaptive automatic test pattern generationIBM·Filed 2019·Granted Oct 27, 2020·0 cites·20 claims
- 1457US10521381B2Self-moderating bus arbitration architectureIBM·Filed 2019·Granted Dec 31, 2019·0 cites·20 claims
- 1557US9086458B2Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidatesIBM·Filed 2013·Granted Jul 21, 2015·1 cites·20 claims
- 1655US10545190B2Circuit structures to resolve random testabilityIBM·Filed 2017·Granted Jan 28, 2020·0 cites·5 claims
- 1755US10386912B2Operating pulsed latches on a variable power supplyIBM·Filed 2017·Granted Aug 20, 2019·0 cites·18 claims
- 1851US9934348B2Adjusting scan connections based on scan control locationsIBM·Filed 2015·Granted Apr 3, 2018·0 cites·20 claims
- 1944US10001523B2Adjusting latency in a scan cellIBM·Filed 2016·Granted Jun 19, 2018·0 cites·20 claims
- 2043US8898604B1Algorithm to identify best Q-gating candidates and a Q-gating cell architecture to satiate the launch-off-shift (LOS) testingIBM·Filed 2013·Granted Nov 25, 2014·0 cites·20 claims
- 2141US8776006B1Delay defect testing of power drop effects in integrated circuitsIBM·Filed 2013·Granted Jul 8, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →