Inventor · disambiguated record
Rachel Gordin
Also filed as: GORDIN RACHEL
14 granted patents·3 pending applications·38 citations·filing 2002–2014
88Inventor score
Top patents by PatentIndex Score
17 records- 0177US8448119B1Method and system for design and modeling of vertical interconnects for 3DI applicationsGORDIN RACHEL·Filed 2012·Granted May 21, 2013·5 cites·19 claims
- 0276US7392490B2System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrateIBM·Filed 2005·Granted Jun 24, 2008·6 cites·14 claims
- 0373US9105627B2Coil inductor for on-chip or on-chip stackSHAPIRO MICHAEL J·Filed 2011·Granted Aug 11, 2015·5 cites·12 claims
- 0470US8793637B2Method and system for design and modeling of vertical interconnects for 3DI applicationsIBM·Filed 2013·Granted Jul 29, 2014·2 cites·18 claims
- 0567US7080340B2Interconnect-aware integrated circuit designIBM·Filed 2003·Granted Jul 18, 2006·13 cites·21 claims
- 0666US9111933B2Stacked through-silicon via (TSV) transformer structureCARPENTER GARY D·Filed 2012·Granted Aug 18, 2015·2 cites·18 claims
- 0761US9397042B2Integrated helical multi-layer inductor structuresIBM·Filed 2014·Granted Jul 19, 2016·1 cites·9 claims
- 0857US7797662B2Method and system for design and modeling of transmission linesIBM·Filed 2007·Granted Sep 14, 2010·1 cites·23 claims
- 0953US8056043B2Capacitance modelingIBM·Filed 2008·Granted Nov 8, 2011·0 cites·18 claims
- 1053US8041546B2Capacitance modelingIBM·Filed 2008·Granted Oct 18, 2011·0 cites·20 claims
- 1148US7454733B2Interconnect-aware methodology for integrated circuit designIBM·Filed 2002·Granted Nov 18, 2008·3 cites·2 claims
- 1248US2015371763A1Nested-helical transformerIBM·Filed 2014·Application pending·0 cites
- 1348US2015371764A1Nested helical inductorIBM·Filed 2014·Application pending·0 cites
- 1443US8347244B2Topologies and methodologies for AMS integrated circuit designIBM·Filed 2007·Granted Jan 1, 2013·0 cites·20 claims
- 1540US8271913B2Method and system for design and modeling of transmission linesCARMON ROI·Filed 2009·Granted Sep 18, 2012·0 cites·6 claims
- 1636US2006072257A1Device and method for reducing dishing of critical on-chip interconnect linesIBM·Filed 2004·Application pending·0 cites
- 1734US8943456B2Layout determining for wide wire on-chip interconnect linesGORDIN RACHEL·Filed 2011·Granted Jan 27, 2015·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →