Inventor · disambiguated record
Raja Prabhu J
Also filed as: J Raja Prabhu
16 granted patents·3 pending applications·22 citations·filing 2015–2025
88Inventor score
Files withSHAOXING YUANFANG SEMICONDUCTOR CO LTD13AURA SEMICONDUCTOR PVT LTD5NINGBO AURA SEMICONDUCTOR CO LTD1
Top patents by PatentIndex Score
19 records- 0190US11588489B1Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lockSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Feb 21, 2023·5 cites·20 claims
- 0283US10514720B1Hitless switching when generating an output clock derived from multiple redundant input clocksAURA SEMICONDUCTOR PVT LTD·Filed 2019·Granted Dec 24, 2019·5 cites·20 claims
- 0382US11592786B1Time-to-digital converter (TDC) measuring phase difference between periodic inputsSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Feb 28, 2023·3 cites·20 claims
- 0480US11736110B2Time-to-digital converter (TDC) to operate with input clock signals with jitterSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Aug 22, 2023·2 cites·20 claims
- 0580US11658667B2Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loopSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted May 23, 2023·2 cites·14 claims
- 0677US12261609B1Inter-PLL communication in a multi-PLL environmentSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2023·Granted Mar 25, 2025·1 cites·20 claims
- 0769US10892765B1Relocking a phase locked loop upon cycle slips between input and feedback clocksAURA SEMICONDUCTOR PVT LTD·Filed 2020·Granted Jan 12, 2021·1 cites·20 claims
- 0868US10700669B2Avoiding very low duty cycles in a divided clock generated by a frequency dividerAURA SEMICONDUCTOR PVT LTD·Filed 2019·Granted Jun 30, 2020·3 cites·15 claims
- 0966US12149255B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2024·Granted Nov 19, 2024·0 cites·6 claims
- 1059US12026028B2Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudesSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Jul 2, 2024·0 cites·20 claims
- 1158US11967965B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Apr 23, 2024·0 cites·13 claims
- 1255US2025323648A1Gain calibration of digital-to-time converter (dtc) used in fractional frequency dividersSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2025·Application pending·0 cites
- 1353US12249996B2Counter design for a time-to-digital converter (TDC)SHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Mar 11, 2025·0 cites·20 claims
- 1453US11711087B2Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loopSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Jul 25, 2023·0 cites·19 claims
- 1552US2025323652A1Reducing non-linearity in a digital-to-time converter (dtc) when an input clock changes between lower and higher periodsSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2024·Application pending·0 cites
- 1640US9742414B2Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loopAURA SEMICONDUCTOR PVT LTD·Filed 2015·Granted Aug 22, 2017·0 cites·20 claims
- 1736US11923864B2Fast switching of output frequency of a phase locked loop (PLL)SHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Mar 5, 2024·0 cites·14 claims
- 1831US11799487B2Fractional sampling-rate converter to generate output samples at a higher rate from input samplesNINGBO AURA SEMICONDUCTOR CO LTD·Filed 2021·Granted Oct 24, 2023·0 cites·21 claims
- 1930US2016336923A1Phase locked loop with low phase-noiseAURA SEMICONDUCTOR PVT LTD·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →