Inventor · disambiguated record
Ravindra M. Kapre
Also filed as: KAPRE RAVINDRA · KAPRE RAVINDRA M · KAPRE RAVINDRA MANOHAR
22 granted patents·331 citations·filing 1999–2022
95Inventor score
Files withCYPRESS SEMICONDUCTOR CORP11LSI LOGIC CORP5Infineon Technologies LLC2KAPRE RAVINDRA M2KOUTNY JR WILLIAM W C1
Top patents by PatentIndex Score
22 records- 0196US8143129B2Integration of non-volatile charge trap memory devices and logic CMOS devicesRAMKUMAR KRISHNASWAMY·Filed 2008·Granted Mar 27, 2012·50 cites·11 claims
- 0295US8093128B2Integration of non-volatile charge trap memory devices and logic CMOS devicesKOUTNY JR WILLIAM W C·Filed 2008·Granted Jan 10, 2012·89 cites·14 claims
- 0392US11017851B1Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereofCYPRESS SEMICONDUCTOR CORP·Filed 2020·Granted May 25, 2021·5 cites·21 claims
- 0490US6413881B1Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting productLSI LOGIC CORP·Filed 2000·Granted Jul 2, 2002·60 cites·10 claims
- 0589US11521962B1ESD protection circuitCYPRESS SEMICONDUCTOR CORP·Filed 2021·Granted Dec 6, 2022·2 cites·20 claims
- 0686US6521549B1Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuitLSI LOGIC CORP·Filed 2000·Granted Feb 18, 2003·39 cites·21 claims
- 0785US7629653B1Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistorsCYPRESS SEMICONDUCTOR CORP·Filed 2007·Granted Dec 8, 2009·10 cites·5 claims
- 0881US8045410B2Memory cell arrayCYPRESS SEMICONDUCTOR CORP·Filed 2009·Granted Oct 25, 2011·6 cites·18 claims
- 0980US6747318B1Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxidesLSI LOGIC CORP·Filed 2001·Granted Jun 8, 2004·34 cites·11 claims
- 1078US7773442B2Memory cell array latchup preventionCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Aug 10, 2010·17 cites·14 claims
- 1176US11810616B2Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereofInfineon Technologies LLC·Filed 2022·Granted Nov 7, 2023·0 cites·18 claims
- 1275US12183395B2Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereofInfineon Technologies LLC·Filed 2022·Granted Dec 31, 2024·0 cites·22 claims
- 1374US8493804B2Memory cell array latchup preventionKAPRE RAVINDRA M·Filed 2011·Granted Jul 23, 2013·3 cites·20 claims
- 1469US11367481B2Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereofCYPRESS SEMICONDUCTOR CORP·Filed 2021·Granted Jun 21, 2022·0 cites·21 claims
- 1568US11355185B2Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereofCYPRESS SEMICONDUCTOR CORP·Filed 2020·Granted Jun 7, 2022·0 cites·24 claims
- 1667US11876090B2ESD protection circuitCYPRESS SEMICONDUCTOR CORP·Filed 2022·Granted Jan 16, 2024·0 cites·14 claims
- 1759US7256087B1Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistorsCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Aug 14, 2007·7 cites·11 claims
- 1855US11581729B2Combined positive and negative voltage electrostatic discharge (ESD) protection clamp with cascoded circuitryCYPRESS SEMICONDUCTOR CORP·Filed 2021·Granted Feb 14, 2023·0 cites·20 claims
- 1955US6656805B2Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuitLSI LOGIC CORP·Filed 2002·Granted Dec 2, 2003·5 cites·10 claims
- 2054US9842629B2Memory cell array latchup preventionCYPRESS SEMICONDUCTOR CORP·Filed 2014·Granted Dec 12, 2017·1 cites·17 claims
- 2140US8252640B1Polycrystalline silicon activation RTAKAPRE RAVINDRA M·Filed 2006·Granted Aug 28, 2012·0 cites·9 claims
- 2234US6759337B1Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrateLSI LOGIC CORP·Filed 1999·Granted Jul 6, 2004·3 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →