Inventor · disambiguated record
Rajeev Malik
Also filed as: MALIK RAJEEV · MALIK RAJEEV KUMAR
26 granted patents·4 pending applications·513 citations·filing 2000–2008
97Inventor score
Files withIBM19INFINEON TECHNOLOGIES AG6INFINEON TECHNOLOGIES CORP3MAUSETH MICHAEL JON1SCHUTZ RONALD J1
Top patents by PatentIndex Score
30 records- 0191US8725597B2Merchant scoring system and transactional databaseMAUSETH MICHAEL JON·Filed 2008·Granted May 13, 2014·104 cites·18 claims
- 0291US7030012B2Method for manufacturing tungsten/polysilicon word line structure in vertical DRAMIBM·Filed 2004·Granted Apr 18, 2006·49 cites·20 claims
- 0390US6635526B1Structure and method for dual work function logic devices in vertical DRAM processINFINEON TECHNOLOGIES AG·Filed 2002·Granted Oct 21, 2003·57 cites·20 claims
- 0489US6897107B2Method for forming TTO nitride liner for improved collar protection and TTO reliabilityINFINEON TECHNOLOGIES CORP·Filed 2003·Granted May 24, 2005·38 cites·10 claims
- 0589US6294423B1Method for forming and filling isolation trenchesINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Sep 25, 2001·54 cites·22 claims
- 0685US7627836B2OPC trimming for performanceIBM·Filed 2005·Granted Dec 1, 2009·15 cites·7 claims
- 0781US6541810B2Modified vertical MOSFET and methods of formation thereofIBM·Filed 2001·Granted Apr 1, 2003·23 cites·6 claims
- 0878US6809368B2TTO nitride liner for improved collar protection and TTO reliabilityIBM·Filed 2001·Granted Oct 26, 2004·15 cites·4 claims
- 0978US6358867B1Orientation independent oxidation of siliconINFINEON TECHNOLOGIES AG·Filed 2000·Granted Mar 19, 2002·45 cites·22 claims
- 1076US7018779B2Apparatus and method to improve resist line roughness in semiconductor wafer processingIBM·Filed 2003·Granted Mar 28, 2006·13 cites·11 claims
- 1175US6509226B1Process for protecting array top oxideIBM·Filed 2000·Granted Jan 21, 2003·15 cites·3 claims
- 1272US6794242B1Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contactsINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 21, 2004·12 cites·14 claims
- 1370US6620676B2Structure and methods for process integration in vertical DRAM cell fabricationIBM·Filed 2001·Granted Sep 16, 2003·14 cites·10 claims
- 1469US6724054B1Self-aligned contact formation using double SiN spacersINFINEON TECHNOLOGIES AG·Filed 2002·Granted Apr 20, 2004·16 cites·14 claims
- 1568US7306983B2Method for forming dual etch stop liner and protective layer in a semiconductor deviceIBM·Filed 2004·Granted Dec 11, 2007·9 cites·22 claims
- 1666US6790739B2Structure and methods for process integration in vertical DRAM cell fabricationIBM·Filed 2003·Granted Sep 14, 2004·11 cites·10 claims
- 1764US7683434B2Preventing cavitation in high aspect ratio dielectric regions of semiconductor deviceIBM·Filed 2008·Granted Mar 23, 2010·2 cites·7 claims
- 1863US6908806B2Gate metal recess for oxidation protection and parasitic capacitance reductionIBM·Filed 2003·Granted Jun 21, 2005·10 cites·7 claims
- 1961US7776695B2Semiconductor device structure having low and high performance devices of same conductive type on same substrateIBM·Filed 2006·Granted Aug 17, 2010·2 cites·17 claims
- 2059US7928571B2Device having dual etch stop liner and reformed silicide layer and related methodsIBM·Filed 2007·Granted Apr 19, 2011·1 cites·11 claims
- 2155US7446395B2Device having dual etch stop liner and protective layerIBM·Filed 2007·Granted Nov 4, 2008·0 cites·8 claims
- 2255US7446062B2Device having dual etch stop liner and reformed silicide layer and related methodsIBM·Filed 2004·Granted Nov 4, 2008·5 cites·16 claims
- 2352US7732270B2Device having enhanced stress state and related methodsIBM·Filed 2008·Granted Jun 8, 2010·0 cites·7 claims
- 2448US6794282B2Three layer aluminum deposition process for high aspect ratio CL contactsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Sep 21, 2004·3 cites·35 claims
- 2548US2006110685A1Apparatus and method to improve resist line roughness in semiconductor wafer processingINFINEON TECHNOLOGIES CORP·Filed 2006·Application pending·0 cites
- 2642US7459384B2Preventing cavitation in high aspect ratio dielectric regions of semiconductor deviceIBM·Filed 2004·Granted Dec 2, 2008·0 cites·15 claims
- 2741US7348635B2Device having enhanced stress state and related methodsIBM·Filed 2004·Granted Mar 25, 2008·0 cites·17 claims
- 2838US2006001162A1Nitride and polysilicon interface with titanium layerSCHUTZ RONALD J·Filed 2005·Application pending·0 cites
- 2938US2004256651A1Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contactsINFINEON TECHNOLOGIES AG·Filed 2004·Application pending·0 cites
- 3035US2004155275A1TTO nitride liner for improved collar protection and TTO reliabilityIBM·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →