Inventor · disambiguated record
Ravi Nair
Also filed as: NAIR RAVI · NAIR RAVI SHANKAR
94 granted patents·7 pending applications·666 citations·filing 2000–2023
99Inventor score
Top patents by PatentIndex Score
101 records- 0194US6779049B2Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanismIBM·Filed 2000·Granted Aug 17, 2004·74 cites·14 claims
- 0293US9448798B1Silent store detection and recording in memory storageIBM·Filed 2016·Granted Sep 20, 2016·8 cites·1 claims
- 0393US7146607B2Method and system for transparent dynamic optimization in a multiprocessing environmentIBM·Filed 2002·Granted Dec 5, 2006·92 cites·45 claims
- 0492US9268704B2Low latency data exchangeIBM·Filed 2013·Granted Feb 23, 2016·15 cites·17 claims
- 0591US6751749B2Method and apparatus for computer system reliabilityIBM·Filed 2001·Granted Jun 15, 2004·78 cites·18 claims
- 0690US7627742B2Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling systemIBM·Filed 2007·Granted Dec 1, 2009·27 cites·17 claims
- 0790US6772368B2Multiprocessor with pair-wise high reliability mode, and method thereforeIBM·Filed 2000·Granted Aug 3, 2004·80 cites·19 claims
- 0888US11016908B2Distributed directory of named data elements in coordination namespaceIBM·Filed 2018·Granted May 25, 2021·5 cites·25 claims
- 0988US10338931B2Approximate synchronization for parallel deep learningIBM·Filed 2016·Granted Jul 2, 2019·7 cites·17 claims
- 1087US9110778B2Address generation in an active memory deviceIBM·Filed 2012·Granted Aug 18, 2015·10 cites·15 claims
- 1186US7017073B2Method and apparatus for fault-tolerance via dual thread crosscheckingIBM·Filed 2002·Granted Mar 21, 2006·42 cites·24 claims
- 1284US11791326B2Memory and logic chip stack with a translator chipIBM·Filed 2021·Granted Oct 17, 2023·1 cites·20 claims
- 1384US9298654B2Local bypass in memory computingIBM·Filed 2013·Granted Mar 29, 2016·6 cites·13 claims
- 1483US7496494B2Method and system for multiprocessor emulation on a multiprocessor host systemIBM·Filed 2002·Granted Feb 24, 2009·31 cites·2 claims
- 1580US9405711B2On-chip traffic prioritization in memoryIBM·Filed 2013·Granted Aug 2, 2016·4 cites·16 claims
- 1680US7805658B2DRAM Cache with on-demand reloadIBM·Filed 2007·Granted Sep 28, 2010·11 cites·17 claims
- 1778US6970982B2Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructionsIBM·Filed 2003·Granted Nov 29, 2005·20 cites·12 claims
- 1876US7509457B2Non-homogeneous multi-processor system with shared memoryIBM·Filed 2005·Granted Mar 24, 2009·4 cites·1 claims
- 1975US8201165B2Virtualizing the execution of homogeneous parallel systems on heterogeneous multiprocessor platformsNAIR RAVI·Filed 2007·Granted Jun 12, 2012·6 cites·10 claims
- 2074US9632777B2Gather/scatter of multiple data elements with packed loading/storing into/from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·3 cites·18 claims
- 2174US9218291B2Implementing selective cache injectionIBM·Filed 2013·Granted Dec 22, 2015·2 cites·11 claims
- 2273US10684958B1Locating node of named data elements in coordination namespaceIBM·Filed 2018·Granted Jun 16, 2020·1 cites·25 claims
- 2373US9569211B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 14, 2017·4 cites·13 claims
- 2473US9389675B2Power management for in-memory computer systemsIBM·Filed 2013·Granted Jul 12, 2016·3 cites·14 claims
- 2572US10049061B2Active memory device gather, scatter, and filterIBM·Filed 2012·Granted Aug 14, 2018·3 cites·14 claims
- 2672US9405712B2On-chip traffic prioritization in memoryIBM·Filed 2013·Granted Aug 2, 2016·2 cites·16 claims
- 2772US6820142B2Token based DMAIBM·Filed 2000·Granted Nov 16, 2004·17 cites·20 claims
- 2871US10831537B2Dynamic update of the number of architected registers assigned to software threads using spill countsIBM·Filed 2017·Granted Nov 10, 2020·1 cites·16 claims
- 2971US9841926B2On-chip traffic prioritization in memoryIBM·Filed 2016·Granted Dec 12, 2017·1 cites·20 claims
- 3071US7797521B2Method, system, and computer program product for path-correlated indirect address predictionsIBM·Filed 2007·Granted Sep 14, 2010·5 cites·19 claims
- 3170US11288208B2Access of named data elements in coordination namespaceIBM·Filed 2018·Granted Mar 29, 2022·1 cites·20 claims
- 3270US10915460B2Coordination namespace processingIBM·Filed 2018·Granted Feb 9, 2021·1 cites·25 claims
- 3370US10572263B2Executing a composite VLIW instruction having a scalar atom that indicates an iteration of executionIBM·Filed 2016·Granted Feb 25, 2020·1 cites·21 claims
- 3470US9575756B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 21, 2017·2 cites·13 claims
- 3570US8719548B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessorALTMAN ERIK RICHTER·Filed 2011·Granted May 6, 2014·3 cites·10 claims
- 3670US8108843B2Hybrid mechanism for more efficient emulation and method thereforNAIR RAVI·Filed 2002·Granted Jan 31, 2012·13 cites·23 claims
- 3770US6938148B2Managing load and store operations using a storage management unit with data flow architectureIBM·Filed 2000·Granted Aug 30, 2005·15 cites·55 claims
- 3870US6907477B2Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processorsIBM·Filed 2004·Granted Jun 14, 2005·11 cites·11 claims
- 3969US8578351B2Hybrid mechanism for more efficient emulation and method thereforNAIR RAVI·Filed 2011·Granted Nov 5, 2013·2 cites·7 claims
- 4067US7953588B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessor hostIBM·Filed 2002·Granted May 31, 2011·11 cites·31 claims
- 4167US7818624B2Processor bus for performance monitoring with digestsIBM·Filed 2008·Granted Oct 19, 2010·2 cites·31 claims
- 4267US6898261B1Method and apparatus for monitoring event occurrencesIBM·Filed 2003·Granted May 24, 2005·14 cites·30 claims
- 4366US11328221B2Hybrid model for short text classification with imbalanced dataIBM·Filed 2019·Granted May 10, 2022·1 cites·20 claims
- 4466US7409597B2Processor bus for performance monitoring with digestsIBM·Filed 2007·Granted Aug 5, 2008·2 cites·20 claims
- 4565US9870340B2Multithreading in vector processorsIBM·Filed 2015·Granted Jan 16, 2018·1 cites·15 claims
- 4665US9274971B2Low latency data exchangeIBM·Filed 2012·Granted Mar 1, 2016·1 cites·17 claims
- 4765US8990620B2Exposed-pipeline processing element with rollbackIBM·Filed 2012·Granted Mar 24, 2015·1 cites·19 claims
- 4864US9582466B2Vector register fileFLEISCHER BRUCE M·Filed 2012·Granted Feb 28, 2017·1 cites·17 claims
- 4963US9329664B2Power management for a computer systemIBM·Filed 2013·Granted May 3, 2016·1 cites·10 claims
- 5062US11275614B2Dynamic update of the number of architected registers assigned to software threads using spill countsIBM·Filed 2019·Granted Mar 15, 2022·0 cites·20 claims
Showing the top 50 of 101 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →