Inventor · disambiguated record
Rajesh Patel
Also filed as: PATEL RAJESH · PATEL RAJESH B · PATEL RAJESH BHIKHUBHAI
50 granted patents·14 pending applications·1,263 citations·filing 1995–2025
99Inventor score
Top patents by PatentIndex Score
64 records- 0195US7579964B2Method for intelligent parking/pollution and surveillance control systemNATTEL GROUP INC·Filed 2007·Granted Aug 25, 2009·57 cites·11 claims
- 0295US7321317B2Method for intelligent parking/pollution and surveillance control systemNATTEL GROUP INC·Filed 2006·Granted Jan 22, 2008·70 cites·16 claims
- 0395US7065349B2Method for automobile safe wireless communicationsNATTEL GROUP INC·Filed 2003·Granted Jun 20, 2006·123 cites·6 claims
- 0494US7738831B2Method for automobile safe wireless communicationsNATTEL GROUP INC·Filed 2007·Granted Jun 15, 2010·34 cites·35 claims
- 0594US7236776B2Method for automobile safe wireless communicationsNATTEL GROUP INC·Filed 2006·Granted Jun 26, 2007·37 cites·16 claims
- 0687US7071839B2Method for total intelligent parking/pollution and surveillance control systemNATTEL GROUP INC·Filed 2003·Granted Jul 4, 2006·45 cites·18 claims
- 0785US7230545B2Automobile communication and registry systemNATTEL GROUP INC·Filed 2003·Granted Jun 12, 2007·68 cites·14 claims
- 0885US6119203AMechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing systemMOTOROLA INC·Filed 1998·Granted Sep 12, 2000·129 cites·14 claims
- 0980US6463511B2System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory modelINTEL CORP·Filed 2000·Granted Oct 8, 2002·27 cites·30 claims
- 1080US5802572AWrite-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cacheIBM·Filed 1996·Granted Sep 1, 1998·90 cites·19 claims
- 1179US6678807B2System and method for multiple store buffer forwarding in a system with a restrictive memory modelINTEL CORP·Filed 2000·Granted Jan 13, 2004·26 cites·20 claims
- 1277US7062638B2Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the storesINTEL CORP·Filed 2000·Granted Jun 13, 2006·25 cites·26 claims
- 1377US6269427B1Multiple load miss handling in a cache memory systemIBM·Filed 1999·Granted Jul 31, 2001·77 cites·20 claims
- 1475US6611900B2System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory modelINTEL CORP·Filed 2002·Granted Aug 26, 2003·19 cites·20 claims
- 1574US7564485B2Method for deactivating an image capturing device when present in a restricted or prohibited zoneNATTEL GROUP INC·Filed 2003·Granted Jul 21, 2009·11 cites·13 claims
- 1672US9710385B2Method and apparatus for accessing physical memory from a CPU or processing element in a high performance mannerINTEL CORP·Filed 2013·Granted Jul 18, 2017·2 cites·18 claims
- 1770US8289850B2Interconnect bandwidth throttlerHACKING LANCE·Filed 2011·Granted Oct 16, 2012·2 cites·8 claims
- 1870US5860107AProcessor and method for store gathering through merged store operationsIBM·Filed 1996·Granted Jan 12, 1999·57 cites·25 claims
- 1969US8018496B2Method for deactivating an image capturing device when present in a restricted or prohibited zoneNATH SANJEEV·Filed 2009·Granted Sep 13, 2011·2 cites·20 claims
- 2068US9060024B2Security event data normalizationPATEL RAJESH·Filed 2009·Granted Jun 16, 2015·3 cites·14 claims
- 2167US8050177B2Interconnect bandwidth throttlerINTEL CORP·Filed 2008·Granted Nov 1, 2011·3 cites·10 claims
- 2263US7877619B2Power mode control method and circuitryRACHAKONDA RAMANA·Filed 2007·Granted Jan 25, 2011·3 cites·20 claims
- 2363US7385484B2Method for automobile registry control systemNATH SANJEEV·Filed 2003·Granted Jun 10, 2008·23 cites·17 claims
- 2460US5809526AData processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operationIBM·Filed 1996·Granted Sep 15, 1998·35 cites·5 claims
- 2559US10282300B2Accessing physical memory from a CPU or processing element in a high performance mannerINTEL CORP·Filed 2017·Granted May 7, 2019·0 cites·20 claims
- 2659US5873123AProcessor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entriesIBM·Filed 1996·Granted Feb 16, 1999·39 cites·17 claims
- 2757US8392728B2Reducing idle leakage power in an ICHACKING LANCE·Filed 2006·Granted Mar 5, 2013·2 cites·4 claims
- 2857US5737749AMethod and system for dynamically sharing cache capacity in a microprocessorIBM·Filed 1996·Granted Apr 7, 1998·40 cites·16 claims
- 2956US5802556AMethod and apparatus for correcting misaligned instruction dataIBM·Filed 1996·Granted Sep 1, 1998·30 cites·12 claims
- 3056US2025252247A1Computer implemented accessibility systems and methodsINNSIGHT COM INC·Filed 2025·Application pending·0 cites
- 3155US5737751ACache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing systemIBM·Filed 1996·Granted Apr 7, 1998·29 cites·8 claims
- 3252US7739483B2Method and apparatus for increasing load bandwidthINTEL CORP·Filed 2001·Granted Jun 15, 2010·2 cites·33 claims
- 3352US7451046B2Imminent collision warning system and methodNATH SANJEEV·Filed 2004·Granted Nov 11, 2008·6 cites·20 claims
- 3452US7269711B2Methods and apparatus for address generation in processorsINTEL CORP·Filed 2003·Granted Sep 11, 2007·3 cites·41 claims
- 3552US2022316889A1System and method for trip planningPATEL RAJESH·Filed 2021·Application pending·0 cites
- 3652US2021241395A1System and method for trip planningPATEL RAJESH·Filed 2021·Application pending·0 cites
- 3751US7612659B2Method for intelligent crescendo systemNATTEL GROUP INC·Filed 2006·Granted Nov 3, 2009·0 cites·20 claims
- 3850US7013366B2Parallel search technique for store operationsINTEL CORP·Filed 2002·Granted Mar 14, 2006·2 cites·30 claims
- 3950US2009134988A1Imminent collision warning system and methodNATTEL GROUP INC·Filed 2008·Application pending·0 cites
- 4049US6321303B1Dynamically modifying queued transactions in a cache memory systemIBM·Filed 1999·Granted Nov 20, 2001·22 cites·20 claims
- 4148US5765191AMethod for implementing a four-way least recently used (LRU) mechanism in high-performanceIBM·Filed 1996·Granted Jun 9, 1998·20 cites·8 claims
- 4247US7075422B2Method for intelligent crescendo systemNATTEL GROUP INC·Filed 2003·Granted Jul 11, 2006·0 cites·8 claims
- 4347US5802340AMethod and system of executing speculative store instructions in a parallel processing computer systemIBM·Filed 1995·Granted Sep 1, 1998·20 cites·10 claims
- 4446US5974505AMethod and system for reducing power consumption of a non-blocking cache within a data processing systemIBM·Filed 1997·Granted Oct 26, 1999·15 cites·11 claims
- 4546US2011163862A1Imminent collision warning system and methodNATTEL GROUP INC·Filed 2011·Application pending·0 cites
- 4645US12216986B2Computer implemented accessibility systems and methodsINNSIGHT COM INC·Filed 2020·Granted Feb 4, 2025·0 cites·20 claims
- 4745US9280473B2Method and apparatus for accessing physical memory from a CPU or processing element in a high performance mannerMONDAL SANJOY K·Filed 2004·Granted Mar 8, 2016·0 cites·17 claims
- 4845US5787479AMethod and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operationIBM·Filed 1996·Granted Jul 28, 1998·17 cites·11 claims
- 4945US2004019753A1System and method for multiple store buffer forwarding in a system with a restrictive memory modelINTEL CORP·Filed 2003·Application pending·0 cites
- 5045US2006021021A1Security event data normalizationPATEL RAJESH·Filed 2005·Application pending·0 cites
Showing the top 50 of 64 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →